diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long')
30 files changed, 34841 insertions, 34816 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 6d2c4821a..4852a1186 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.893221 # Number of seconds simulated -sim_ticks 1893220881500 # Number of ticks simulated -final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.893228 # Number of seconds simulated +sim_ticks 1893227633000 # Number of ticks simulated +final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25399 # Simulator instruction rate (inst/s) -host_op_rate 25399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856404595 # Simulator tick rate (ticks/s) -host_mem_usage 393548 # Number of bytes of host memory used -host_seconds 2210.66 # Real time elapsed on the host -sim_insts 56147815 # Number of instructions simulated -sim_ops 56147815 # Number of ops (including micro ops) simulated +host_inst_rate 25790 # Simulator instruction rate (inst/s) +host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 869674472 # Simulator tick rate (ticks/s) +host_mem_usage 393476 # Number of bytes of host memory used +host_seconds 2176.94 # Real time elapsed on the host +sim_insts 56143729 # Number of instructions simulated +sim_ops 56143729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404812 # Number of read requests accepted -system.physmem.writeReqs 118228 # Number of write requests accepted -system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404826 # Number of read requests accepted +system.physmem.writeReqs 118235 # Number of write requests accepted +system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::0 25487 # Per bank write bursts +system.physmem.perBankRdBursts::1 25708 # Per bank write bursts system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25775 # Per bank write bursts -system.physmem.perBankRdBursts::4 25223 # Per bank write bursts +system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::4 25224 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24583 # Per bank write bursts -system.physmem.perBankRdBursts::8 25108 # Per bank write bursts +system.physmem.perBankRdBursts::7 24580 # Per bank write bursts +system.physmem.perBankRdBursts::8 25111 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25518 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24528 # Per bank write bursts -system.physmem.perBankRdBursts::13 25564 # Per bank write bursts -system.physmem.perBankRdBursts::14 25798 # Per bank write bursts -system.physmem.perBankRdBursts::15 25721 # Per bank write bursts -system.physmem.perBankWrBursts::0 7829 # Per bank write bursts -system.physmem.perBankWrBursts::1 7671 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6944 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7237 # Per bank write bursts -system.physmem.perBankWrBursts::9 6873 # Per bank write bursts -system.physmem.perBankWrBursts::10 7386 # Per bank write bursts -system.physmem.perBankWrBursts::11 6888 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::11 24876 # Per bank write bursts +system.physmem.perBankRdBursts::12 24529 # Per bank write bursts +system.physmem.perBankRdBursts::13 25563 # Per bank write bursts +system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::15 25723 # Per bank write bursts +system.physmem.perBankWrBursts::0 7828 # Per bank write bursts +system.physmem.perBankWrBursts::1 7672 # Per bank write bursts +system.physmem.perBankWrBursts::2 8070 # Per bank write bursts +system.physmem.perBankWrBursts::3 7747 # Per bank write bursts +system.physmem.perBankWrBursts::4 7316 # Per bank write bursts +system.physmem.perBankWrBursts::5 6943 # Per bank write bursts +system.physmem.perBankWrBursts::6 6787 # Per bank write bursts +system.physmem.perBankWrBursts::7 6421 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 6874 # Per bank write bursts +system.physmem.perBankWrBursts::10 7389 # Per bank write bursts +system.physmem.perBankWrBursts::11 6891 # Per bank write bursts +system.physmem.perBankWrBursts::12 7084 # Per bank write bursts +system.physmem.perBankWrBursts::13 8012 # Per bank write bursts +system.physmem.perBankWrBursts::14 7998 # Per bank write bursts system.physmem.perBankWrBursts::15 7945 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 68 # Number of times write queue was full causing retry -system.physmem.totGap 1893211891000 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1893218679000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404812 # Read request sizes (log2) +system.physmem.readPktSize::6 404826 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118235 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,206 +149,205 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads -system.physmem.totQLat 5895300250 # Total ticks spent queuing -system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads +system.physmem.totQLat 5894702000 # Total ticks spent queuing +system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing -system.physmem.readRowHits 363810 # Number of row buffer hits during reads -system.physmem.writeRowHits 95775 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing +system.physmem.readRowHits 363769 # Number of row buffer hits during reads +system.physmem.writeRowHits 95780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619631.18 # Average gap between requests -system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.054730 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states -system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.269176 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15264339 # Number of BP lookups -system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits +system.physmem.avgGap 3619498.83 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.096553 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states +system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.231588 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15259378 # Number of BP lookups +system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9321681 # DTB read hits -system.cpu.dtb.read_misses 17691 # DTB read misses +system.cpu.dtb.read_hits 9322510 # DTB read hits +system.cpu.dtb.read_misses 17386 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764795 # DTB read accesses -system.cpu.dtb.write_hits 6394158 # DTB write hits -system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298776 # DTB write accesses -system.cpu.dtb.data_hits 15715839 # DTB hits -system.cpu.dtb.data_misses 20133 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063571 # DTB accesses -system.cpu.itb.fetch_hits 4020046 # ITB hits -system.cpu.itb.fetch_misses 6280 # ITB misses -system.cpu.itb.fetch_acv 699 # ITB acv -system.cpu.itb.fetch_accesses 4026326 # ITB accesses +system.cpu.dtb.read_accesses 764595 # DTB read accesses +system.cpu.dtb.write_hits 6393584 # DTB write hits +system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.write_acv 158 # DTB write access violations +system.cpu.dtb.write_accesses 298734 # DTB write accesses +system.cpu.dtb.data_hits 15716094 # DTB hits +system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.data_acv 369 # DTB access violations +system.cpu.dtb.data_accesses 1063329 # DTB accesses +system.cpu.itb.fetch_hits 4018414 # ITB hits +system.cpu.itb.fetch_misses 6313 # ITB misses +system.cpu.itb.fetch_acv 710 # ITB acv +system.cpu.itb.fetch_accesses 4024727 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,29 +360,29 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12752 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12750 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193121889 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193068084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56147815 # Number of instructions committed -system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.439526 # CPI: cycles per instruction -system.cpu.ipc 0.290738 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56143729 # Number of instructions committed +system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.438818 # CPI: cycles per instruction +system.cpu.ipc 0.290798 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -413,36 +412,36 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56147815 # Class of committed instruction +system.cpu.op_class_0::total 56143729 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -450,7 +449,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -459,31 +458,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192465 # number of callpals executed +system.cpu.kern.callpal::total 192387 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394246 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. +system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394486 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -491,153 +490,153 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits -system.cpu.dcache.overall_hits::total 13563977 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses -system.cpu.dcache.overall_misses::total 1670044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits +system.cpu.dcache.overall_hits::total 13563915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses +system.cpu.dcache.overall_misses::total 1670224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks -system.cpu.dcache.writebacks::total 837664 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks +system.cpu.dcache.writebacks::total 837775 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477105 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1476860 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -645,319 +644,320 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 104 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19233043 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19233043 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19233043 # number of overall hits -system.cpu.icache.overall_hits::total 19233043 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1477790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1477790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1477790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1477790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1477790 # number of overall misses -system.cpu.icache.overall_misses::total 1477790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20696583500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20696583500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20696583500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20696583500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20696583500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20696583500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20710833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20710833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20710833 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20710833 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20710833 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20710833 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071353 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071353 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits +system.cpu.icache.overall_hits::total 19221455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses +system.cpu.icache.overall_misses::total 1477546 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks -system.cpu.icache.writebacks::total 1477105 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339628 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.171233 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6812996000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 268.308875 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5785.000603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905690 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks +system.cpu.icache.writebacks::total 1476860 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 339644 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46341016 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46341016 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837664 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837664 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1476525 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1476525 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187358 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187358 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461386 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1461386 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818548 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 818548 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1461386 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1005906 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2467292 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1461386 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1005906 # number of overall hits -system.cpu.l2cache.overall_hits::total 2467292 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits +system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116652 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116652 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16348 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16348 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272226 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272226 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16348 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388878 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405226 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16348 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388878 # number of overall misses -system.cpu.l2cache.overall_misses::total 405226 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 331000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10499091500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10499091500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1618484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1618484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21963269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21963269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1618484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32462361000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34080845000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1618484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32462361000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34080845000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837664 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837664 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1476525 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1476525 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses +system.cpu.l2cache.overall_misses::total 405239 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477734 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1477734 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090774 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1090774 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1477734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1394784 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2872518 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1477734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1394784 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2872518 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383711 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383711 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011063 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011063 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249571 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249571 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011063 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278809 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141070 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011063 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278809 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141070 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76716 # number of writebacks -system.cpu.l2cache.writebacks::total 76716 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks +system.cpu.l2cache.writebacks::total 76723 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116652 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116652 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16348 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16348 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272226 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272226 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388878 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388878 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405226 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340242 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340255 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +971,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1002,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1050,14 +1050,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1074,19 +1074,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1098,14 +1098,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1114,75 +1114,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295653 # Transaction distribution +system.membus.trans_dist::ReadResp 295677 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution -system.membus.trans_dist::CleanEvict 262245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution +system.membus.trans_dist::CleanEvict 262254 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116520 # Transaction distribution -system.membus.trans_dist::ReadExResp 116520 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 116510 # Transaction distribution +system.membus.trans_dist::ReadExResp 116510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution +system.membus.trans_dist::BadAddressError 23 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 127 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 434 # Total snoops (count) +system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 561 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463510 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram +system.membus.snoop_fanout::samples 463523 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463510 # Request fanout histogram -system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463523 # Request fanout histogram +system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1214,28 +1215,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d900375a8..53cfb4ebd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907549 # Number of seconds simulated -sim_ticks 1907549438500 # Number of ticks simulated -final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.909484 # Number of seconds simulated +sim_ticks 1909483951500 # Number of ticks simulated +final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237406 # Simulator instruction rate (inst/s) -host_op_rate 237406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7990338524 # Simulator tick rate (ticks/s) -host_mem_usage 342872 # Number of bytes of host memory used -host_seconds 238.73 # Real time elapsed on the host -sim_insts 56676315 # Number of instructions simulated -sim_ops 56676315 # Number of ops (including micro ops) simulated +host_inst_rate 164890 # Simulator instruction rate (inst/s) +host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5556117262 # Simulator tick rate (ticks/s) +host_mem_usage 341236 # Number of bytes of host memory used +host_seconds 343.67 # Real time elapsed on the host +sim_insts 56668174 # Number of instructions simulated +sim_ops 56668174 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411070 # Number of read requests accepted -system.physmem.writeReqs 123616 # Number of write requests accepted -system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411061 # Number of read requests accepted +system.physmem.writeReqs 123600 # Number of write requests accepted +system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26240 # Per bank write bursts -system.physmem.perBankRdBursts::1 25986 # Per bank write bursts -system.physmem.perBankRdBursts::2 25958 # Per bank write bursts -system.physmem.perBankRdBursts::3 25690 # Per bank write bursts -system.physmem.perBankRdBursts::4 25582 # Per bank write bursts -system.physmem.perBankRdBursts::5 25570 # Per bank write bursts -system.physmem.perBankRdBursts::6 25628 # Per bank write bursts -system.physmem.perBankRdBursts::7 25343 # Per bank write bursts +system.physmem.perBankRdBursts::0 26241 # Per bank write bursts +system.physmem.perBankRdBursts::1 25988 # Per bank write bursts +system.physmem.perBankRdBursts::2 25972 # Per bank write bursts +system.physmem.perBankRdBursts::3 25684 # Per bank write bursts +system.physmem.perBankRdBursts::4 25579 # Per bank write bursts +system.physmem.perBankRdBursts::5 25567 # Per bank write bursts +system.physmem.perBankRdBursts::6 25634 # Per bank write bursts +system.physmem.perBankRdBursts::7 25346 # Per bank write bursts system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25698 # Per bank write bursts -system.physmem.perBankRdBursts::10 25929 # Per bank write bursts -system.physmem.perBankRdBursts::11 25525 # Per bank write bursts +system.physmem.perBankRdBursts::9 25694 # Per bank write bursts +system.physmem.perBankRdBursts::10 25928 # Per bank write bursts +system.physmem.perBankRdBursts::11 25514 # Per bank write bursts system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25420 # Per bank write bursts -system.physmem.perBankRdBursts::14 25099 # Per bank write bursts -system.physmem.perBankRdBursts::15 25608 # Per bank write bursts -system.physmem.perBankWrBursts::0 8587 # Per bank write bursts +system.physmem.perBankRdBursts::13 25422 # Per bank write bursts +system.physmem.perBankRdBursts::14 25093 # Per bank write bursts +system.physmem.perBankRdBursts::15 25620 # Per bank write bursts +system.physmem.perBankWrBursts::0 8582 # Per bank write bursts system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7940 # Per bank write bursts -system.physmem.perBankWrBursts::3 7436 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7415 # Per bank write bursts -system.physmem.perBankWrBursts::6 7544 # Per bank write bursts -system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::2 7941 # Per bank write bursts +system.physmem.perBankWrBursts::3 7423 # Per bank write bursts +system.physmem.perBankWrBursts::4 7276 # Per bank write bursts +system.physmem.perBankWrBursts::5 7412 # Per bank write bursts +system.physmem.perBankWrBursts::6 7548 # Per bank write bursts +system.physmem.perBankWrBursts::7 7160 # Per bank write bursts system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7639 # Per bank write bursts -system.physmem.perBankWrBursts::10 7820 # Per bank write bursts -system.physmem.perBankWrBursts::11 7739 # Per bank write bursts -system.physmem.perBankWrBursts::12 8260 # Per bank write bursts -system.physmem.perBankWrBursts::13 7848 # Per bank write bursts -system.physmem.perBankWrBursts::14 7518 # Per bank write bursts -system.physmem.perBankWrBursts::15 7790 # Per bank write bursts +system.physmem.perBankWrBursts::9 7637 # Per bank write bursts +system.physmem.perBankWrBursts::10 7817 # Per bank write bursts +system.physmem.perBankWrBursts::11 7733 # Per bank write bursts +system.physmem.perBankWrBursts::12 8265 # Per bank write bursts +system.physmem.perBankWrBursts::13 7849 # Per bank write bursts +system.physmem.perBankWrBursts::14 7512 # Per bank write bursts +system.physmem.perBankWrBursts::15 7803 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 73 # Number of times write queue was full causing retry -system.physmem.totGap 1907545081500 # Total gap between requests +system.physmem.numWrRetry 80 # Number of times write queue was full causing retry +system.physmem.totGap 1909479571500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411070 # Read request sizes (log2) +system.physmem.readPktSize::6 411061 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123616 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123600 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -159,206 +159,205 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads -system.physmem.totQLat 8174654750 # Total ticks spent queuing -system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads +system.physmem.totQLat 8180795500 # Total ticks spent queuing +system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing -system.physmem.readRowHits 370634 # Number of row buffer hits during reads -system.physmem.writeRowHits 99508 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing +system.physmem.readRowHits 370615 # Number of row buffer hits during reads +system.physmem.writeRowHits 99546 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes -system.physmem.avgGap 3567598.71 # Average gap between requests +system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes +system.physmem.avgGap 3571383.68 # Average gap between requests system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.583627 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states -system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.455703 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16746871 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits +system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.578716 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states +system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.436414 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16749334 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9412979 # DTB read hits -system.cpu0.dtb.read_misses 34328 # DTB read misses -system.cpu0.dtb.read_acv 621 # DTB read access violations -system.cpu0.dtb.read_accesses 567042 # DTB read accesses -system.cpu0.dtb.write_hits 5709982 # DTB write hits -system.cpu0.dtb.write_misses 8326 # DTB write misses -system.cpu0.dtb.write_acv 453 # DTB write access violations -system.cpu0.dtb.write_accesses 184750 # DTB write accesses -system.cpu0.dtb.data_hits 15122961 # DTB hits -system.cpu0.dtb.data_misses 42654 # DTB misses -system.cpu0.dtb.data_acv 1074 # DTB access violations -system.cpu0.dtb.data_accesses 751792 # DTB accesses -system.cpu0.itb.fetch_hits 1307701 # ITB hits -system.cpu0.itb.fetch_misses 6903 # ITB misses -system.cpu0.itb.fetch_acv 605 # ITB acv -system.cpu0.itb.fetch_accesses 1314604 # ITB accesses +system.cpu0.dtb.read_hits 9423503 # DTB read hits +system.cpu0.dtb.read_misses 34044 # DTB read misses +system.cpu0.dtb.read_acv 602 # DTB read access violations +system.cpu0.dtb.read_accesses 567323 # DTB read accesses +system.cpu0.dtb.write_hits 5707426 # DTB write hits +system.cpu0.dtb.write_misses 8375 # DTB write misses +system.cpu0.dtb.write_acv 432 # DTB write access violations +system.cpu0.dtb.write_accesses 185068 # DTB write accesses +system.cpu0.dtb.data_hits 15130929 # DTB hits +system.cpu0.dtb.data_misses 42419 # DTB misses +system.cpu0.dtb.data_acv 1034 # DTB access violations +system.cpu0.dtb.data_accesses 752391 # DTB accesses +system.cpu0.itb.fetch_hits 1309826 # ITB hits +system.cpu0.itb.fetch_misses 6979 # ITB misses +system.cpu0.itb.fetch_acv 608 # ITB acv +system.cpu0.itb.fetch_accesses 1316805 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -371,271 +370,272 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119482029 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119453997 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 168885 16.81% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 486832 48.47% 65.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300564 29.92% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26620 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21571 2.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9721676 18.48% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5686986 10.81% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122455 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110756 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued -system.cpu0.iq.rate 0.440369 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1004472 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019091 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219643746 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569416 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53310020 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 308067 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued +system.cpu0.iq.rate 0.440485 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3539791 # number of nop insts executed -system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258466 # Number of branches executed -system.cpu0.iew.exec_stores 5735212 # Number of stores executed -system.cpu0.iew.exec_rate 0.434663 # Inst execution rate -system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26224773 # num instructions producing a value -system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3535809 # number of nop insts executed +system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258108 # Number of branches executed +system.cpu0.iew.exec_stores 5732729 # Number of stores executed +system.cpu0.iew.exec_rate 0.434781 # Inst execution rate +system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26231692 # num instructions producing a value +system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49598051 # Number of instructions committed -system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49593272 # Number of instructions committed +system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266916 # Number of memory references committed -system.cpu0.commit.loads 7864510 # Number of loads committed -system.cpu0.commit.membars 192309 # Number of memory barriers committed -system.cpu0.commit.branches 7509354 # Number of branches committed -system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632192 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.refs 13266986 # Number of memory references committed +system.cpu0.commit.loads 7864361 # Number of loads committed +system.cpu0.commit.membars 192313 # Number of memory barriers committed +system.cpu0.commit.branches 7507748 # Number of branches committed +system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632222 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction @@ -663,324 +663,324 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943636 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5298998 10.68% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169680194 # The number of ROB reads -system.cpu0.rob.rob_writes 120607262 # The number of ROB writes -system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46714728 # Number of Instructions Simulated -system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68002319 # number of integer regfile reads -system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1253317 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169631516 # The number of ROB reads +system.cpu0.rob.rob_writes 120597460 # The number of ROB writes +system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46709842 # Number of Instructions Simulated +system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads +system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1252644 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits -system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses -system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks -system.cpu0.dcache.writebacks::total 737739 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses +system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks +system.cpu0.dcache.writebacks::total 737573 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 894430 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 892272 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits -system.cpu0.icache.overall_hits::total 7502081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses -system.cpu0.icache.overall_misses::total 949140 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits +system.cpu0.icache.overall_hits::total 7503325 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses +system.cpu0.icache.overall_misses::total 945376 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks -system.cpu0.icache.writebacks::total 894430 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4438770 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks +system.cpu0.icache.writebacks::total 892272 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4441555 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431495 # DTB read hits -system.cpu1.dtb.read_misses 15697 # DTB read misses -system.cpu1.dtb.read_acv 126 # DTB read access violations -system.cpu1.dtb.read_accesses 432376 # DTB read accesses -system.cpu1.dtb.write_hits 1439190 # DTB write hits -system.cpu1.dtb.write_misses 3913 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 163232 # DTB write accesses -system.cpu1.dtb.data_hits 3870685 # DTB hits -system.cpu1.dtb.data_misses 19610 # DTB misses -system.cpu1.dtb.data_acv 194 # DTB access violations -system.cpu1.dtb.data_accesses 595608 # DTB accesses -system.cpu1.itb.fetch_hits 677547 # ITB hits -system.cpu1.itb.fetch_misses 3477 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 681024 # ITB accesses +system.cpu1.dtb.read_hits 2431988 # DTB read hits +system.cpu1.dtb.read_misses 15687 # DTB read misses +system.cpu1.dtb.read_acv 78 # DTB read access violations +system.cpu1.dtb.read_accesses 432427 # DTB read accesses +system.cpu1.dtb.write_hits 1439876 # DTB write hits +system.cpu1.dtb.write_misses 3853 # DTB write misses +system.cpu1.dtb.write_acv 69 # DTB write access violations +system.cpu1.dtb.write_accesses 163205 # DTB write accesses +system.cpu1.dtb.data_hits 3871864 # DTB hits +system.cpu1.dtb.data_misses 19540 # DTB misses +system.cpu1.dtb.data_acv 147 # DTB access violations +system.cpu1.dtb.data_accesses 595632 # DTB accesses +system.cpu1.itb.fetch_hits 677957 # ITB hits +system.cpu1.itb.fetch_misses 3440 # ITB misses +system.cpu1.itb.fetch_acv 149 # ITB acv +system.cpu1.itb.fetch_accesses 681397 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -993,584 +993,584 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17543632 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17559475 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33628 10.29% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 174409 53.35% 63.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 103464 31.65% 95.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 7989 2.44% 97.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7397 2.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2510604 21.88% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1425191 12.42% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45057 0.39% 97.01% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43675 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued -system.cpu1.iq.rate 0.653939 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326887 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028493 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39721827 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 225631 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11674105 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120495 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued +system.cpu1.iq.rate 0.653242 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650401 # number of nop insts executed -system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1687752 # Number of branches executed -system.cpu1.iew.exec_stores 1449670 # Number of stores executed -system.cpu1.iew.exec_rate 0.643141 # Inst execution rate -system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5287384 # num instructions producing a value -system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650640 # number of nop insts executed +system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1689156 # Number of branches executed +system.cpu1.iew.exec_stores 1450305 # Number of stores executed +system.cpu1.iew.exec_rate 0.642403 # Inst execution rate +system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5286560 # num instructions producing a value +system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10447204 # Number of instructions committed -system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10444029 # Number of instructions committed +system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3352983 # Number of memory references committed -system.cpu1.commit.loads 1987935 # Number of loads committed -system.cpu1.commit.membars 48912 # Number of memory barriers committed -system.cpu1.commit.branches 1499265 # Number of branches committed -system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163857 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1992105 19.07% 83.63% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1323963 12.67% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3355674 # Number of memory references committed +system.cpu1.commit.loads 1990378 # Number of loads committed +system.cpu1.commit.membars 48933 # Number of memory barriers committed +system.cpu1.commit.branches 1499197 # Number of branches committed +system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163891 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction -system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28744557 # The number of ROB reads -system.cpu1.rob.rob_writes 26537349 # The number of ROB writes -system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9961587 # Number of Instructions Simulated -system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14521611 # number of integer regfile reads -system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes -system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads -system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 130966 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction +system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28763808 # The number of ROB reads +system.cpu1.rob.rob_writes 26546353 # The number of ROB writes +system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9958332 # Number of Instructions Simulated +system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads +system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes +system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads +system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 131073 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits -system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses -system.cpu1.dcache.overall_misses::total 533959 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks -system.cpu1.dcache.writebacks::total 84601 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses +system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits +system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses +system.cpu1.dcache.overall_misses::total 533406 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks +system.cpu1.dcache.writebacks::total 84598 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256896 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256867 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits -system.cpu1.icache.overall_hits::total 1710963 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses -system.cpu1.icache.overall_misses::total 269604 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits +system.cpu1.icache.overall_hits::total 1711658 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses +system.cpu1.icache.overall_misses::total 269479 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks -system.cpu1.icache.writebacks::total 256896 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks +system.cpu1.icache.writebacks::total 256867 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1583,12 +1583,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54611 # Transaction distribution -system.iobus.trans_dist::WriteResp 54611 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54619 # Transaction distribution +system.iobus.trans_dist::WriteResp 54619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1597,11 +1597,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1610,50 +1610,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1662,14 +1662,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1686,19 +1686,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1710,14 +1710,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1726,200 +1726,200 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345941 # number of replacements -system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use -system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345934 # number of replacements +system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use +system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38390429 # Number of tag accesses -system.l2c.tags.data_accesses 38390429 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38356372 # Number of tag accesses +system.l2c.tags.data_accesses 38356372 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits -system.l2c.demand_hits::total 2120409 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 881644 # number of overall hits -system.l2c.overall_hits::cpu0.data 868221 # number of overall hits -system.l2c.overall_hits::cpu1.inst 255533 # number of overall hits -system.l2c.overall_hits::cpu1.data 115011 # number of overall hits -system.l2c.overall_hits::total 2120409 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits +system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits +system.l2c.overall_hits::cpu0.data 867710 # number of overall hits +system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits +system.l2c.overall_hits::cpu1.data 115068 # number of overall hits +system.l2c.overall_hits::total 2117738 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109595 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12065 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121660 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13405 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1909 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15314 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272577 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1964 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274541 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13405 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 382172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1909 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14029 # number of demand (read+write) misses -system.l2c.demand_misses::total 411515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13405 # number of overall misses -system.l2c.overall_misses::cpu0.data 382172 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1909 # number of overall misses -system.l2c.overall_misses::cpu1.data 14029 # number of overall misses -system.l2c.overall_misses::total 411515 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 332000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 449000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 11349867000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1517430000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12867297000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1343054000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 191509000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1534563000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22206710000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 230127000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 22436837000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1343054000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 33556577000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 191509000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1747557000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 36838697000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1343054000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 33556577000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 191509000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1747557000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 36838697000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 822340 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 822340 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 875169 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 875169 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2869 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1499 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4368 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 969 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 255583 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43028 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298611 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 895049 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 257442 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1152491 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 994810 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 86012 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1080822 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 895049 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1250393 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 257442 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 129040 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2531924 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 895049 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1250393 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 257442 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 129040 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2531924 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002091 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003336 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.002518 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.001032 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428804 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.280399 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.407420 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014977 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007415 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013288 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273999 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022834 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254011 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014977 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305642 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007415 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.108718 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.162531 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014977 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305642 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007415 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.108718 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.162531 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23400 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 40818.181818 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103561.905196 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125771.239121 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 105764.400789 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100190.525923 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 100319.015191 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 100206.543033 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81469.493024 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117172.606925 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 81724.904477 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 89519.694300 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 89519.694300 # average overall miss latency +system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses +system.l2c.demand_misses::total 411506 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses +system.l2c.overall_misses::cpu0.data 382165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses +system.l2c.overall_misses::cpu1.data 14030 # number of overall misses +system.l2c.overall_misses::total 411506 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82096 # number of writebacks -system.l2c.writebacks::total 82096 # number of writebacks +system.l2c.writebacks::writebacks 82080 # number of writebacks +system.l2c.writebacks::total 82080 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits @@ -1929,249 +1929,251 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 109595 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12065 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121660 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13404 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1892 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15296 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272577 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1964 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 274541 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13404 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 382172 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1892 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411497 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13404 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 382172 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1892 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411497 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13059 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20254 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 272000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 95500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 367500 # number of UpgradeReq MSHR miss cycles +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10253916501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1396780000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11650696501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1208926000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 171260500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1380186500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19486691503 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 210487000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19697178503 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1208926000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 29740608004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 171260500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1607267000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 32728061504 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1208926000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 29740608004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 171260500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1607267000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 32728061504 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469664500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39141500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1508806000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469664500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39141500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1508806000 # number of overall MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002091 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003336 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002518 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001032 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428804 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280399 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.407420 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013272 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273999 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022834 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254011 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162523 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162523 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19100 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297167 # Transaction distribution -system.membus.trans_dist::WriteReq 13059 # Transaction distribution -system.membus.trans_dist::WriteResp 13059 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution -system.membus.trans_dist::CleanEvict 263125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution +system.membus.trans_dist::ReadResp 297263 # Transaction distribution +system.membus.trans_dist::WriteReq 13067 # Transaction distribution +system.membus.trans_dist::WriteResp 13067 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution +system.membus.trans_dist::CleanEvict 263134 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121953 # Transaction distribution -system.membus.trans_dist::ReadExResp 121548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution -system.membus.trans_dist::BadAddressError 44 # Transaction distribution +system.membus.trans_dist::ReadExReq 121851 # Transaction distribution +system.membus.trans_dist::ReadExResp 121443 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution +system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 134 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12507 # Total snoops (count) +system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12662 # Total snoops (count) system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485548 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram +system.membus.snoop_fanout::samples 485569 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485548 # Request fanout histogram -system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485569 # Request fanout histogram +system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382362 # Total snoops (count) -system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382331 # Total snoops (count) +system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2203,142 +2205,142 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163475 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches +system.cpu0.kern.callpal::total 163481 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1070 system.cpu0.kern.mode_good::user 1070 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3350 # number of times the context was actually changed +system.cpu0.kern.swap_context 3352 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed -system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed +system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54577 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches -system.cpu1.kern.mode_switch::user 669 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 888 -system.cpu1.kern.mode_good::user 669 -system.cpu1.kern.mode_good::idle 219 -system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 54607 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches +system.cpu1.kern.mode_switch::user 670 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 670 +system.cpu1.kern.mode_good::idle 220 +system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1229 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1231 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index bb54c4dfa..5af666630 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865012 # Number of seconds simulated -sim_ticks 1865011607500 # Number of ticks simulated -final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865010 # Number of seconds simulated +sim_ticks 1865009748000 # Number of ticks simulated +final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239114 # Simulator instruction rate (inst/s) -host_op_rate 239113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8418978943 # Simulator tick rate (ticks/s) -host_mem_usage 338260 # Number of bytes of host memory used -host_seconds 221.52 # Real time elapsed on the host -sim_insts 52969539 # Number of instructions simulated -sim_ops 52969539 # Number of ops (including micro ops) simulated +host_inst_rate 235871 # Simulator instruction rate (inst/s) +host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8303287371 # Simulator tick rate (ticks/s) +host_mem_usage 337912 # Number of bytes of host memory used +host_seconds 224.61 # Real time elapsed on the host +sim_insts 52979108 # Number of instructions simulated +sim_ops 52979108 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403805 # Number of read requests accepted -system.physmem.writeReqs 117412 # Number of write requests accepted -system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403803 # Number of read requests accepted +system.physmem.writeReqs 117441 # Number of write requests accepted +system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25445 # Per bank write bursts -system.physmem.perBankRdBursts::1 25617 # Per bank write bursts -system.physmem.perBankRdBursts::2 25496 # Per bank write bursts -system.physmem.perBankRdBursts::3 25620 # Per bank write bursts -system.physmem.perBankRdBursts::4 25117 # Per bank write bursts -system.physmem.perBankRdBursts::5 25178 # Per bank write bursts -system.physmem.perBankRdBursts::6 24740 # Per bank write bursts -system.physmem.perBankRdBursts::7 24558 # Per bank write bursts -system.physmem.perBankRdBursts::8 25032 # Per bank write bursts -system.physmem.perBankRdBursts::9 25302 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25006 # Per bank write bursts -system.physmem.perBankRdBursts::12 24377 # Per bank write bursts -system.physmem.perBankRdBursts::13 25425 # Per bank write bursts -system.physmem.perBankRdBursts::14 25800 # Per bank write bursts -system.physmem.perBankRdBursts::15 25695 # Per bank write bursts -system.physmem.perBankWrBursts::0 7802 # Per bank write bursts -system.physmem.perBankWrBursts::1 7592 # Per bank write bursts -system.physmem.perBankWrBursts::2 7774 # Per bank write bursts -system.physmem.perBankWrBursts::3 7602 # Per bank write bursts -system.physmem.perBankWrBursts::4 7239 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 6741 # Per bank write bursts -system.physmem.perBankWrBursts::7 6416 # Per bank write bursts -system.physmem.perBankWrBursts::8 7149 # Per bank write bursts -system.physmem.perBankWrBursts::9 6926 # Per bank write bursts -system.physmem.perBankWrBursts::10 7200 # Per bank write bursts -system.physmem.perBankWrBursts::11 7003 # Per bank write bursts -system.physmem.perBankWrBursts::12 6957 # Per bank write bursts -system.physmem.perBankWrBursts::13 7880 # Per bank write bursts -system.physmem.perBankWrBursts::14 8017 # Per bank write bursts +system.physmem.perBankRdBursts::0 25444 # Per bank write bursts +system.physmem.perBankRdBursts::1 25611 # Per bank write bursts +system.physmem.perBankRdBursts::2 25628 # Per bank write bursts +system.physmem.perBankRdBursts::3 25719 # Per bank write bursts +system.physmem.perBankRdBursts::4 25100 # Per bank write bursts +system.physmem.perBankRdBursts::5 25088 # Per bank write bursts +system.physmem.perBankRdBursts::6 24758 # Per bank write bursts +system.physmem.perBankRdBursts::7 24649 # Per bank write bursts +system.physmem.perBankRdBursts::8 24903 # Per bank write bursts +system.physmem.perBankRdBursts::9 25188 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25005 # Per bank write bursts +system.physmem.perBankRdBursts::12 24375 # Per bank write bursts +system.physmem.perBankRdBursts::13 25430 # Per bank write bursts +system.physmem.perBankRdBursts::14 25804 # Per bank write bursts +system.physmem.perBankRdBursts::15 25697 # Per bank write bursts +system.physmem.perBankWrBursts::0 7804 # Per bank write bursts +system.physmem.perBankWrBursts::1 7583 # Per bank write bursts +system.physmem.perBankWrBursts::2 7900 # Per bank write bursts +system.physmem.perBankWrBursts::3 7698 # Per bank write bursts +system.physmem.perBankWrBursts::4 7224 # Per bank write bursts +system.physmem.perBankWrBursts::5 7092 # Per bank write bursts +system.physmem.perBankWrBursts::6 6759 # Per bank write bursts +system.physmem.perBankWrBursts::7 6515 # Per bank write bursts +system.physmem.perBankWrBursts::8 7053 # Per bank write bursts +system.physmem.perBankWrBursts::9 6824 # Per bank write bursts +system.physmem.perBankWrBursts::10 7197 # Per bank write bursts +system.physmem.perBankWrBursts::11 7005 # Per bank write bursts +system.physmem.perBankWrBursts::12 6955 # Per bank write bursts +system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::14 8018 # Per bank write bursts system.physmem.perBankWrBursts::15 7915 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1865006319500 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 1865004470500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403805 # Read request sizes (log2) +system.physmem.readPktSize::6 403803 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117412 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117441 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -149,117 +149,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 7801574500 # Total ticks spent queuing -system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 7817102750 # Total ticks spent queuing +system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s @@ -268,88 +266,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing -system.physmem.readRowHits 364428 # Number of row buffer hits during reads -system.physmem.writeRowHits 95430 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes -system.physmem.avgGap 3578176.31 # Average gap between requests -system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.372821 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states -system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.404390 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19540652 # Number of BP lookups -system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits +system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing +system.physmem.readRowHits 364427 # Number of row buffer hits during reads +system.physmem.writeRowHits 95317 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes +system.physmem.avgGap 3577987.41 # Average gap between requests +system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.351146 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states +system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.364142 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19556212 # Number of BP lookups +system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11133148 # DTB read hits -system.cpu.dtb.read_misses 49550 # DTB read misses -system.cpu.dtb.read_acv 604 # DTB read access violations -system.cpu.dtb.read_accesses 995639 # DTB read accesses -system.cpu.dtb.write_hits 6779390 # DTB write hits -system.cpu.dtb.write_misses 12217 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 345330 # DTB write accesses -system.cpu.dtb.data_hits 17912538 # DTB hits -system.cpu.dtb.data_misses 61767 # DTB misses -system.cpu.dtb.data_acv 1023 # DTB access violations -system.cpu.dtb.data_accesses 1340969 # DTB accesses -system.cpu.itb.fetch_hits 1814760 # ITB hits -system.cpu.itb.fetch_misses 10379 # ITB misses -system.cpu.itb.fetch_acv 753 # ITB acv -system.cpu.itb.fetch_accesses 1825139 # ITB accesses +system.cpu.dtb.read_hits 11131129 # DTB read hits +system.cpu.dtb.read_misses 49734 # DTB read misses +system.cpu.dtb.read_acv 613 # DTB read access violations +system.cpu.dtb.read_accesses 995788 # DTB read accesses +system.cpu.dtb.write_hits 6783534 # DTB write hits +system.cpu.dtb.write_misses 12230 # DTB write misses +system.cpu.dtb.write_acv 435 # DTB write access violations +system.cpu.dtb.write_accesses 345368 # DTB write accesses +system.cpu.dtb.data_hits 17914663 # DTB hits +system.cpu.dtb.data_misses 61964 # DTB misses +system.cpu.dtb.data_acv 1048 # DTB access violations +system.cpu.dtb.data_accesses 1341156 # DTB accesses +system.cpu.itb.fetch_hits 1815343 # ITB hits +system.cpu.itb.fetch_misses 10369 # ITB misses +system.cpu.itb.fetch_acv 759 # ITB acv +system.cpu.itb.fetch_accesses 1825712 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -364,154 +362,154 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12878 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129626512 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129653253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued @@ -535,97 +533,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued -system.cpu.iq.rate 0.467035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued +system.cpu.iq.rate 0.467155 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3982483 # number of nop insts executed -system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed -system.cpu.iew.exec_branches 9384105 # Number of branches executed -system.cpu.iew.exec_stores 6811811 # Number of stores executed -system.cpu.iew.exec_rate 0.460445 # Inst execution rate -system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29769052 # num instructions producing a value -system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3983673 # number of nop insts executed +system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed +system.cpu.iew.exec_branches 9387402 # Number of branches executed +system.cpu.iew.exec_stores 6815981 # Number of stores executed +system.cpu.iew.exec_rate 0.460540 # Inst execution rate +system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29779151 # num instructions producing a value +system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value +system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56159642 # Number of instructions committed -system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169799 # Number of instructions committed +system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15467967 # Number of memory references committed -system.cpu.commit.loads 9090756 # Number of loads committed -system.cpu.commit.membars 226364 # Number of memory barriers committed -system.cpu.commit.branches 8439956 # Number of branches committed +system.cpu.commit.refs 15470470 # Number of memory references committed +system.cpu.commit.loads 9092521 # Number of loads committed +system.cpu.commit.membars 226360 # Number of memory barriers committed +system.cpu.commit.branches 8440690 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52009640 # Number of committed integer instructions. -system.cpu.commit.function_calls 740476 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. +system.cpu.commit.function_calls 740566 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -655,37 +653,37 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction -system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187788618 # The number of ROB reads -system.cpu.rob.rob_writes 139599579 # The number of ROB writes -system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52969539 # Number of Instructions Simulated -system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77875050 # number of integer regfile reads -system.cpu.int_regfile_writes 42594378 # number of integer regfile writes -system.cpu.fp_regfile_reads 166655 # number of floating regfile reads -system.cpu.fp_regfile_writes 175866 # number of floating regfile writes -system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads -system.cpu.misc_regfile_writes 939499 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405977 # number of replacements +system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction +system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187851195 # The number of ROB reads +system.cpu.rob.rob_writes 139687376 # The number of ROB writes +system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979108 # Number of Instructions Simulated +system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77910051 # number of integer regfile reads +system.cpu.int_regfile_writes 42617580 # number of integer regfile writes +system.cpu.fp_regfile_reads 166665 # number of floating regfile reads +system.cpu.fp_regfile_writes 175716 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads +system.cpu.misc_regfile_writes 939513 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405851 # number of replacements system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy @@ -695,506 +693,507 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits -system.cpu.dcache.overall_hits::total 12198735 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses -system.cpu.dcache.overall_misses::total 3783444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits +system.cpu.dcache.overall_hits::total 12200800 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses +system.cpu.dcache.overall_misses::total 3784033 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks -system.cpu.dcache.writebacks::total 844399 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks +system.cpu.dcache.writebacks::total 844182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1076759 # number of replacements -system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1077480 # number of replacements +system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11005677 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11005677 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits -system.cpu.icache.overall_hits::total 8782144 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses -system.cpu.icache.overall_misses::total 1145952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits +system.cpu.icache.overall_hits::total 8783075 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses +system.cpu.icache.overall_misses::total 1146854 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1076759 # number of writebacks -system.cpu.icache.writebacks::total 1076759 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68371 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68371 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68371 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68371 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks +system.cpu.icache.writebacks::total 1077480 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 338614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65420.353665 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4559964 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.283241 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6414398000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 255.266765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5296.205124 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.913527 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5602 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58570 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40121077 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40121077 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 844399 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 844399 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1076079 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1076079 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 69 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 69 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 98 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 98 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185276 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185276 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062141 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1062141 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832063 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 832063 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1062141 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1017339 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2079480 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1062141 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1017339 # number of overall hits -system.cpu.l2cache.overall_hits::total 2079480 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 114725 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 114725 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15044 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 15044 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274467 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 274467 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15044 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389192 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404236 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15044 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389192 # number of overall misses -system.cpu.l2cache.overall_misses::total 404236 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 418500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 418500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12044968500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12044968500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1516847000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1516847000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22392456000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22392456000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1516847000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34437424500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35954271500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1516847000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34437424500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35954271500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 844399 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 844399 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1076079 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1076079 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 78 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 98 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 98 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300001 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300001 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077185 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1077185 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106530 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1106530 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1077185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1406531 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2483716 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1077185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1406531 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2483716 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382415 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382415 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248043 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248043 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013966 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276703 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.162755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276703 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.162755 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 46500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 46500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits +system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses +system.cpu.l2cache.overall_misses::total 404244 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 75900 # number of writebacks -system.cpu.l2cache.writebacks::total 75900 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks +system.cpu.l2cache.writebacks::total 75929 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15043 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389192 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404235 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15043 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389192 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404235 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 328500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 328500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10897718500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10897718500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1366325500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1366325500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19653014500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19653014500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339563 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339553 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1207,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1239,46 +1238,46 @@ system.iobus.pkt_size_system.bridge.master::total 44156 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1287,14 +1286,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1311,19 +1310,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1335,14 +1334,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1351,75 +1350,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296573 # Transaction distribution +system.membus.trans_dist::ReadResp 296601 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution -system.membus.trans_dist::CleanEvict 262094 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution +system.membus.trans_dist::CleanEvict 262065 # Transaction distribution system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114597 # Transaction distribution -system.membus.trans_dist::ReadExResp 114597 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution -system.membus.trans_dist::BadAddressError 40 # Transaction distribution +system.membus.trans_dist::ReadExReq 114568 # Transaction distribution +system.membus.trans_dist::ReadExResp 114568 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution +system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 438 # Total snoops (count) -system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462498 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram +system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 563 # Total snoops (count) +system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 462504 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462498 # Request fanout histogram -system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462504 # Request fanout histogram +system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1451,29 +1451,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed @@ -1487,11 +1487,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1514,19 +1514,19 @@ system.cpu.kern.callpal::rti 5106 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191988 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1908 system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index c0e015b81..37e31e615 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848927 # Number of seconds simulated -sim_ticks 2848926718000 # Number of ticks simulated -final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848913 # Number of seconds simulated +sim_ticks 2848912955000 # Number of ticks simulated +final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263408 # Simulator instruction rate (inst/s) -host_op_rate 318982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5866973599 # Simulator tick rate (ticks/s) -host_mem_usage 626336 # Number of bytes of host memory used -host_seconds 485.59 # Real time elapsed on the host -sim_insts 127907365 # Number of instructions simulated -sim_ops 154893549 # Number of ops (including micro ops) simulated +host_inst_rate 258856 # Simulator instruction rate (inst/s) +host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5762698171 # Simulator tick rate (ticks/s) +host_mem_usage 627144 # Number of bytes of host memory used +host_seconds 494.37 # Real time elapsed on the host +sim_insts 127970828 # Number of instructions simulated +sim_ops 154969713 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 9536 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1676224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1355764 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8486720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 229952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 664980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 417216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12842440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1676224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 229952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1906176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9074368 # Number of bytes written to this memory +system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 149 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10411 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 201207 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141787 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 146178 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3347 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 588370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 475886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2978918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 233414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 146447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4507817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 588370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 669086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3185188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3191353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3185188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 588370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 482037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2978918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 233428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 146447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7699170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 201207 # Number of read requests accepted -system.physmem.writeReqs 146178 # Number of write requests accepted -system.physmem.readBursts 201207 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 146178 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12868352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 9104640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12842440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9091932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201104 # Number of read requests accepted +system.physmem.writeReqs 145983 # Number of write requests accepted +system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12387 # Per bank write bursts -system.physmem.perBankRdBursts::1 12818 # Per bank write bursts -system.physmem.perBankRdBursts::2 13574 # Per bank write bursts -system.physmem.perBankRdBursts::3 13051 # Per bank write bursts -system.physmem.perBankRdBursts::4 15332 # Per bank write bursts -system.physmem.perBankRdBursts::5 12655 # Per bank write bursts -system.physmem.perBankRdBursts::6 12896 # Per bank write bursts -system.physmem.perBankRdBursts::7 13054 # Per bank write bursts -system.physmem.perBankRdBursts::8 12485 # Per bank write bursts -system.physmem.perBankRdBursts::9 12494 # Per bank write bursts -system.physmem.perBankRdBursts::10 11451 # Per bank write bursts -system.physmem.perBankRdBursts::11 10701 # Per bank write bursts -system.physmem.perBankRdBursts::12 11947 # Per bank write bursts -system.physmem.perBankRdBursts::13 12784 # Per bank write bursts -system.physmem.perBankRdBursts::14 11815 # Per bank write bursts -system.physmem.perBankRdBursts::15 11624 # Per bank write bursts -system.physmem.perBankWrBursts::0 9013 # Per bank write bursts +system.physmem.perBankRdBursts::0 12429 # Per bank write bursts +system.physmem.perBankRdBursts::1 12794 # Per bank write bursts +system.physmem.perBankRdBursts::2 13696 # Per bank write bursts +system.physmem.perBankRdBursts::3 13190 # Per bank write bursts +system.physmem.perBankRdBursts::4 15337 # Per bank write bursts +system.physmem.perBankRdBursts::5 12894 # Per bank write bursts +system.physmem.perBankRdBursts::6 12741 # Per bank write bursts +system.physmem.perBankRdBursts::7 13088 # Per bank write bursts +system.physmem.perBankRdBursts::8 12333 # Per bank write bursts +system.physmem.perBankRdBursts::9 12486 # Per bank write bursts +system.physmem.perBankRdBursts::10 11357 # Per bank write bursts +system.physmem.perBankRdBursts::11 10671 # Per bank write bursts +system.physmem.perBankRdBursts::12 11888 # Per bank write bursts +system.physmem.perBankRdBursts::13 12773 # Per bank write bursts +system.physmem.perBankRdBursts::14 11762 # Per bank write bursts +system.physmem.perBankRdBursts::15 11515 # Per bank write bursts +system.physmem.perBankWrBursts::0 8987 # Per bank write bursts system.physmem.perBankWrBursts::1 9459 # Per bank write bursts -system.physmem.perBankWrBursts::2 10048 # Per bank write bursts -system.physmem.perBankWrBursts::3 9447 # Per bank write bursts -system.physmem.perBankWrBursts::4 8653 # Per bank write bursts -system.physmem.perBankWrBursts::5 8898 # Per bank write bursts -system.physmem.perBankWrBursts::6 9273 # Per bank write bursts -system.physmem.perBankWrBursts::7 9228 # Per bank write bursts -system.physmem.perBankWrBursts::8 8869 # Per bank write bursts -system.physmem.perBankWrBursts::9 8977 # Per bank write bursts -system.physmem.perBankWrBursts::10 8270 # Per bank write bursts -system.physmem.perBankWrBursts::11 7926 # Per bank write bursts -system.physmem.perBankWrBursts::12 8743 # Per bank write bursts -system.physmem.perBankWrBursts::13 8906 # Per bank write bursts -system.physmem.perBankWrBursts::14 8530 # Per bank write bursts -system.physmem.perBankWrBursts::15 8020 # Per bank write bursts +system.physmem.perBankWrBursts::2 10102 # Per bank write bursts +system.physmem.perBankWrBursts::3 9553 # Per bank write bursts +system.physmem.perBankWrBursts::4 8641 # Per bank write bursts +system.physmem.perBankWrBursts::5 9022 # Per bank write bursts +system.physmem.perBankWrBursts::6 9160 # Per bank write bursts +system.physmem.perBankWrBursts::7 9289 # Per bank write bursts +system.physmem.perBankWrBursts::8 8726 # Per bank write bursts +system.physmem.perBankWrBursts::9 8906 # Per bank write bursts +system.physmem.perBankWrBursts::10 8219 # Per bank write bursts +system.physmem.perBankWrBursts::11 7897 # Per bank write bursts +system.physmem.perBankWrBursts::12 8731 # Per bank write bursts +system.physmem.perBankWrBursts::13 8920 # Per bank write bursts +system.physmem.perBankWrBursts::14 8491 # Per bank write bursts +system.physmem.perBankWrBursts::15 7959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 92 # Number of times write queue was full causing retry -system.physmem.totGap 2848926179000 # Total gap between requests +system.physmem.numWrRetry 98 # Number of times write queue was full causing retry +system.physmem.totGap 2848912399000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 554 # Read request sizes (log2) +system.physmem.readPktSize::2 556 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200625 # Read request sizes (log2) +system.physmem.readPktSize::6 200520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141592 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,178 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 295 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.676495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.021398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.276619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45910 51.12% 51.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18733 20.86% 71.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6663 7.42% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3737 4.16% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2991 3.33% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 1.70% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 943 1.05% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1048 1.17% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8251 9.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89804 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.382976 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 553.950604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7082 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7084 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.081875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.511113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.183489 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5975 84.35% 84.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 419 5.91% 90.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 0.96% 91.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 50 0.71% 91.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 261 3.68% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.30% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.18% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.24% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.14% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.11% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 144 2.03% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.13% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.11% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7084 # Writes before turning the bus around for reads -system.physmem.totQLat 9521946881 # Total ticks spent queuing -system.physmem.totMemAccLat 13291971881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1005340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47356.85 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads +system.physmem.totQLat 9366475580 # Total ticks spent queuing +system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66106.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing -system.physmem.readRowHits 166479 # Number of row buffer hits during reads -system.physmem.writeRowHits 87044 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.18 # Row buffer hit rate for writes -system.physmem.avgGap 8201062.74 # Average gap between requests -system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339864000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 180642000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 755176380 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 386379180 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5802201600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5394350610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 323555040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11564942040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8568107520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 670261966035 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 703579433835 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.962980 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2836248193267 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 586826713 # Time in different power states -system.physmem_0.memoryStateTime::REF 2465512000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2788574898250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 22312648073 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9624892520 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25361940444 # Time in different power states -system.physmem_1.actEnergy 301343700 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 160164180 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 680449140 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 356218020 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5736435120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5416162800 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 310781280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10711678260 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8807078880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 670588805775 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 703071916065 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.784837 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2836233678907 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 556712196 # Time in different power states -system.physmem_1.memoryStateTime::REF 2438058000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2789808007000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22935120354 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9698204397 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 23490616053 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing +system.physmem.readRowHits 166422 # Number of row buffer hits during reads +system.physmem.writeRowHits 86905 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes +system.physmem.avgGap 8208064.26 # Average gap between requests +system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.980538 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states +system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states +system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.743143 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states +system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -375,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20832099 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13651765 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1014112 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13085676 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8745572 # Number of BTB hits +system.cpu0.branchPred.lookups 20830846 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.833169 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3412344 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 213562 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 762387 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 580471 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 181916 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 99152 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -428,58 +428,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65584 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65584 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44931 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20653 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65584 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65584 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65584 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6815 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 9573.930789 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 6808 99.90% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66699 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5268 77.30% 77.30% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1547 22.70% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6815 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65584 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65584 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6815 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6815 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17333612 # DTB read hits -system.cpu0.dtb.read_misses 59171 # DTB read misses -system.cpu0.dtb.write_hits 14536785 # DTB write hits -system.cpu0.dtb.write_misses 6413 # DTB write misses +system.cpu0.dtb.read_hits 17337178 # DTB read hits +system.cpu0.dtb.read_misses 60105 # DTB read misses +system.cpu0.dtb.write_hits 14536732 # DTB write hits +system.cpu0.dtb.write_misses 6594 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17392783 # DTB read accesses -system.cpu0.dtb.write_accesses 14543198 # DTB write accesses +system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17397283 # DTB read accesses +system.cpu0.dtb.write_accesses 14543326 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31870397 # DTB hits -system.cpu0.dtb.misses 65584 # DTB misses -system.cpu0.dtb.accesses 31935981 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31873910 # DTB hits +system.cpu0.dtb.misses 66699 # DTB misses +system.cpu0.dtb.accesses 31940609 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,41 +512,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3993 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3993 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3689 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3993 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3993 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3993 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2420 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5199.448662 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 453 18.72% 18.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1764 72.89% 91.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 139 5.74% 97.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 1.12% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4013 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2121 87.64% 87.64% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.36% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2420 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3993 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3993 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2420 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2420 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6413 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38722571 # ITB inst hits -system.cpu0.itb.inst_misses 3993 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38740955 # ITB inst hits +system.cpu0.itb.inst_misses 4013 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -552,804 +554,798 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7056 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38726564 # ITB inst accesses -system.cpu0.itb.hits 38722571 # DTB hits -system.cpu0.itb.misses 3993 # DTB misses -system.cpu0.itb.accesses 38726564 # DTB accesses -system.cpu0.numPwrStateTransitions 3692 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1846 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1496527734.232936 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23959432114.332718 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1066 57.75% 57.75% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 41.87% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses +system.cpu0.itb.hits 38740955 # DTB hits +system.cpu0.itb.misses 4013 # DTB misses +system.cpu0.itb.accesses 38744968 # DTB accesses +system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963466540 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1846 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 86336520606 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 172675597 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 172712897 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79702454 # Number of instructions committed -system.cpu0.committedOps 95912008 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5263315 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1846 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5525206368 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.166503 # CPI: cycles per instruction -system.cpu0.ipc 0.461573 # IPC: instructions per cycle +system.cpu0.committedInsts 79713377 # Number of instructions committed +system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.166674 # CPI: cycles per instruction +system.cpu0.ipc 0.461537 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63720470 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92091 0.10% 66.53% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16805556 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15273907 15.92% 99.99% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95912008 # Class of committed instruction +system.cpu0.op_class_0::total 95922535 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1846 # number of quiesce instructions executed -system.cpu0.tickCycles 120803038 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51872559 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716043 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.070686 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30430864 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 716555 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.468288 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed +system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716918 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.070686 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970841 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.970841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63800570 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63800570 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15847676 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15847676 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13422923 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13422923 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320765 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320765 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365692 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365692 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361178 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29270599 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29270599 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29591364 # number of overall hits -system.cpu0.dcache.overall_hits::total 29591364 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 438302 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 438302 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 581071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 581071 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135874 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135874 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20748 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20748 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20391 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20391 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1019373 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1019373 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1155247 # number of overall misses -system.cpu0.dcache.overall_misses::total 1155247 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6426011500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6426011500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11337499000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11337499000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330321500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330321500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481265000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 481265000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 655500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 655500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 17763510500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17763510500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 17763510500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17763510500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16285978 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16285978 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14003994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456639 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456639 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386440 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386440 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381569 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381569 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30289972 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30289972 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30746611 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30746611 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026913 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026913 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041493 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041493 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297552 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297552 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053690 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053690 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053440 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053440 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033654 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033654 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037573 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037573 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14661.150303 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14661.150303 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19511.383291 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19511.383291 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15920.642954 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15920.642954 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23601.834143 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23601.834143 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits +system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses +system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716044 # number of writebacks -system.cpu0.dcache.writebacks::total 716044 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44411 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44411 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255478 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255478 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14411 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14411 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 299889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 299889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 299889 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 299889 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393891 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 393891 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325593 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325593 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102318 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102318 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20391 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20391 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 719484 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 719484 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 821802 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 821802 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks +system.cpu0.dcache.writebacks::total 716918 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5265212000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5265212000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6193589500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6193589500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1698431500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1698431500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460892000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460892000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 637500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 637500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11458801500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11458801500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13157233000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13157233000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4606601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4606601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4606601500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4606601500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024186 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024186 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023250 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023250 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224068 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224068 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053440 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053440 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023753 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023753 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026728 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026728 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13367.180261 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13367.180261 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19022.489734 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19022.489734 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16599.537716 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885 # average StoreCondReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15926.416015 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16010.222657 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16010.222657 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.385528 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.385528 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115607.235175 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115607.235175 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1964076 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.773099 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36750687 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1964588 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.706562 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6697445000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773099 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1966568 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79395176 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79395176 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36750687 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36750687 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36750687 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36750687 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36750687 # number of overall hits -system.cpu0.icache.overall_hits::total 36750687 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1964601 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1964601 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1964601 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1964601 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1964601 # number of overall misses -system.cpu0.icache.overall_misses::total 1964601 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19791309500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 19791309500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 19791309500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 19791309500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 19791309500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 19791309500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38715288 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38715288 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38715288 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38715288 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38715288 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38715288 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050745 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050745 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050745 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050745 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050745 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050745 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.958783 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.958783 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10073.958783 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10073.958783 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79434387 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79434387 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36766553 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36766553 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36766553 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36766553 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36766553 # number of overall hits +system.cpu0.icache.overall_hits::total 36766553 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1967094 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1967094 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1967094 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1967094 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1967094 # number of overall misses +system.cpu0.icache.overall_misses::total 1967094 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19796906000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 19796906000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 19796906000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 19796906000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 19796906000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 19796906000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38733647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38733647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38733647 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38733647 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38733647 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38733647 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050785 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050785 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050785 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050785 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050785 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050785 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.036594 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.036594 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1964076 # number of writebacks -system.cpu0.icache.writebacks::total 1964076 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1964601 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1964601 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1964601 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1964601 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1964601 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1964601 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1966568 # number of writebacks +system.cpu0.icache.writebacks::total 1966568 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1967094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1967094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1967094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1967094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1967094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1967094 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18809009500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 18809009500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18809009500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 18809009500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18809009500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 18809009500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18813359500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 18813359500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18813359500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 18813359500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18813359500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 18813359500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050745 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050745 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050745 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.959038 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050785 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050785 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050785 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.036848 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843459 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1843558 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 87 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845428 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1845508 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 234570 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 289188 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15635.373554 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2589127 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 304798 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.494567 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 289262 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14528.592543 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.479311 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.075767 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.225933 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.886755 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003997 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063551 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954307 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 228 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 147 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7305 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5549 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.013916 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 91385031 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 91385031 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77639 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5220 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 82859 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481305 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481305 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2156745 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2156745 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222879 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 222879 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1872794 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1872794 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388786 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 388786 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77639 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5220 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1872794 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611665 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2567318 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77639 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5220 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1872794 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611665 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2567318 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 934 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 150 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1084 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56829 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 56829 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20390 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20390 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45892 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 45892 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91807 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 91807 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 113754 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 113754 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 934 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 150 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 91807 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 159646 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 252537 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 934 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 150 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 91807 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 159646 # number of overall misses -system.cpu0.l2cache.overall_misses::total 252537 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 44624500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3518000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 48142500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 45750500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 45750500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9568000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9568000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 607499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 607499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2923141000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2923141000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4535079000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4535079000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3749547498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3749547498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 44624500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3518000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4535079000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6672688498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 11255909998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 44624500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3518000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4535079000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6672688498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 11255909998 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78573 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5370 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 83943 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481305 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481305 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2156745 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2156745 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56829 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56829 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20390 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20390 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268771 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268771 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1964601 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1964601 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 502540 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 502540 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78573 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5370 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1964601 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 771311 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2819855 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78573 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5370 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1964601 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 771311 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2819855 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027933 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.012914 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 2159151 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222970 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 222970 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1875280 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1875280 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389002 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 389002 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78219 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5306 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1875280 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 611972 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2570777 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78219 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5306 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1875280 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 611972 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2570777 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1055 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 176 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1231 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56519 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 56519 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20396 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20396 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46078 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 46078 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91814 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 91814 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 114162 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 114162 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1055 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 176 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 91814 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 160240 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 253285 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1055 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 176 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 91814 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 160240 # number of overall misses +system.cpu0.l2cache.overall_misses::total 253285 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 45088000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4105500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 49193500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 43638000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 43638000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 10254000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 10254000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 591500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 591500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2907293999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2907293999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4520777000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4520777000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3763870996 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3763870996 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 45088000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4105500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4520777000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6671164995 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 11241135495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 45088000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4105500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4520777000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6671164995 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 11241135495 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79274 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5482 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 84756 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481785 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 481785 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 2159151 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 2159151 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56519 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 56519 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20396 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20396 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269048 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269048 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1967094 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1967094 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 503164 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 503164 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79274 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5482 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1967094 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 772212 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2824062 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79274 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5482 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1967094 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 772212 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2824062 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032105 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.170748 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.170748 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046731 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046731 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226358 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226358 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027933 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046731 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.206980 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.089557 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027933 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046731 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.206980 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.089557 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23453.333333 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44411.900369 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 805.055517 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 805.055517 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 469.249632 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 469.249632 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 607499 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 607499 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63696.090822 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63696.090822 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49397.965297 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49397.965297 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32961.895828 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32961.895828 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23453.333333 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49397.965297 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41796.778485 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 44571.330134 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23453.333333 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49397.965297 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41796.778485 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 44571.330134 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171263 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171263 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046675 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046675 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226888 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226888 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032105 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046675 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.207508 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.089688 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032105 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046675 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.207508 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.089688 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23326.704545 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39962.225833 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 772.094340 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 772.094340 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 502.745636 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 502.745636 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63095.056187 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63095.056187 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49238.427691 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49238.427691 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32969.560765 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32969.560765 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 44381.370768 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 44381.370768 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10760 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 232550 # number of writebacks -system.cpu0.l2cache.writebacks::total 232550 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3193 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3193 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 56 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 56 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 400 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 400 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 56 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3593 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3650 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 56 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3593 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3650 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 933 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 150 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1083 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264017 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 264017 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56829 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56829 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20390 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20390 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42699 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42699 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 91751 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 91751 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 113354 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 113354 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 933 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 150 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91751 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156053 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 248887 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 933 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 150 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91751 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156053 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264017 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 512904 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10931 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 232720 # number of writebacks +system.cpu0.l2cache.writebacks::total 232720 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3236 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3236 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 62 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 62 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 399 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 399 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 62 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3635 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3705 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 62 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3635 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3705 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1051 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1223 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 265014 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56519 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56519 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20396 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20396 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42842 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42842 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 91752 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 91752 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 113763 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 113763 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1051 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91752 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156605 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 249580 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1051 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91752 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156605 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 514594 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23854 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23858 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43124 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2618000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41625500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16806240735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16806240735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 985974500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 985974500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 307077498 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 307077498 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 499499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 499499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2171871000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2171871000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3982642000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3982642000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3045418498 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3045418498 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2618000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3982642000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5217289498 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 9241556998 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2618000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3982642000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5217289498 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16806240735 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 26047797733 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43128 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3003500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41677500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16721781964 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 978283000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 978283000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308154500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308154500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 483500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 483500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2153848999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2153848999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3967827500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3967827500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3058327496 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3058327496 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3003500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3967827500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5212176495 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 9221681495 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3003500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3967827500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5212176495 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25943463459 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4441867000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4739533000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4442744500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4740410500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4441867000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4739533000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.012902 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4442744500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4740410500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014430 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158868 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158868 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046702 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.225562 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.225562 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088262 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159236 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159236 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046643 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226095 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226095 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088376 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181890 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 499499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 499499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5514708 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2778846 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 220650 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216436 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4214 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 117829 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2634124 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714129 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2198813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 313152 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88836 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287887 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1964601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602822 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3087 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5899831 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2594741 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13052 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164810 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8672434 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251644992 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99451448 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314292 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351432212 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 940964 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19090924 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3779220 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076318 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.269673 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3495013 92.48% 92.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 279993 7.41% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4214 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3779220 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5504902494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115882925 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2952081467 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1226789533 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7686990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 86252968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19393527 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6185527 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 769783 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9956759 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3606289 # Number of BTB hits +system.cpu1.branchPred.lookups 19376501 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.219507 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8702764 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 566393 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3646067 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3582470 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 63597 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23601 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1379,58 +1375,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26638 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26638 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20208 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6430 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26638 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26638 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26638 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8690.810286 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 2656 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26 0.97% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1849661032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1849661032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1849661032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1998 74.44% 74.44% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 686 25.56% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2684 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26638 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 26236 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26638 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2684 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 29322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11320530 # DTB read hits -system.cpu1.dtb.read_misses 24586 # DTB read misses -system.cpu1.dtb.write_hits 7061626 # DTB write hits -system.cpu1.dtb.write_misses 2052 # DTB write misses +system.cpu1.dtb.read_hits 11335471 # DTB read hits +system.cpu1.dtb.read_misses 23997 # DTB read misses +system.cpu1.dtb.write_hits 7067505 # DTB write hits +system.cpu1.dtb.write_misses 2239 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1992 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11345116 # DTB read accesses -system.cpu1.dtb.write_accesses 7063678 # DTB write accesses +system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11359468 # DTB read accesses +system.cpu1.dtb.write_accesses 7069744 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18382156 # DTB hits -system.cpu1.dtb.misses 26638 # DTB misses -system.cpu1.dtb.accesses 18408794 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18402976 # DTB hits +system.cpu1.dtb.misses 26236 # DTB misses +system.cpu1.dtb.accesses 18429212 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1460,45 +1461,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2499 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2499 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2445 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2319 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2499 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4984.320484 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 166 14.72% 14.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 634 56.21% 70.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 206 18.26% 89.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.34% 93.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 1.95% 95.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.42% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1850303532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1850303532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1850303532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 963 85.37% 85.37% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.63% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1128 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2499 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1128 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1128 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3627 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39699373 # ITB inst hits -system.cpu1.itb.inst_misses 2499 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39707544 # ITB inst hits +system.cpu1.itb.inst_misses 2445 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1507,45 +1508,45 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1101 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1838 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39701872 # ITB inst accesses -system.cpu1.itb.hits 39699373 # DTB hits -system.cpu1.itb.misses 2499 # DTB misses -system.cpu1.itb.accesses 39701872 # DTB accesses -system.cpu1.numPwrStateTransitions 5523 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2762 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1010212132.618392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25718871891.755051 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1964 71.11% 71.11% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.75% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses +system.cpu1.itb.hits 39707544 # DTB hits +system.cpu1.itb.misses 2445 # DTB misses +system.cpu1.itb.accesses 39709989 # DTB accesses +system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949979704076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2762 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58720807708 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 117445100 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 117416330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48204911 # Number of instructions committed -system.cpu1.committedOps 58981541 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5132548 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2762 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5579768700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.436372 # CPI: cycles per instruction -system.cpu1.ipc 0.410446 # IPC: instructions per cycle +system.cpu1.committedInsts 48257451 # Number of instructions committed +system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.433123 # CPI: cycles per instruction +system.cpu1.ipc 0.410994 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40607989 68.85% 68.85% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45709 0.08% 68.93% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction @@ -1571,715 +1572,721 @@ system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Cl system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11146731 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7175909 12.17% 100.00% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 58981541 # Class of committed instruction +system.cpu1.op_class_0::total 59047178 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2762 # number of quiesce instructions executed -system.cpu1.tickCycles 94223774 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 23221326 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 197231 # number of replacements -system.cpu1.dcache.tags.tagsinuse 476.160023 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17961880 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 197583 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.908023 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91326739500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.160023 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.930000 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.930000 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36815018 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36815018 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10942799 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10942799 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6773317 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6773317 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50710 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50710 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80304 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80304 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71747 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71747 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17716116 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17716116 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17766826 # number of overall hits -system.cpu1.dcache.overall_hits::total 17766826 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 150509 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 150509 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145770 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145770 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30651 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30651 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23697 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23697 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296279 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 326930 # number of overall misses -system.cpu1.dcache.overall_misses::total 326930 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2503108000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2503108000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4131089000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4131089000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325863000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325863000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557327500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557327500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 612000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 612000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6634197000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6634197000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6634197000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6634197000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11093308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11093308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6919087 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6919087 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97264 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97264 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95444 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95444 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18012395 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18012395 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18093756 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18093756 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013568 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013568 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021068 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021068 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.376728 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.376728 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174371 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174371 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248282 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248282 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016449 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018069 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018069 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19213.620283 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19213.620283 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23518.905347 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23518.905347 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 197406 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits +system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses +system.cpu1.dcache.overall_misses::total 326977 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 197231 # number of writebacks -system.cpu1.dcache.writebacks::total 197231 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5831 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5831 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53065 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53065 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12062 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12062 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58896 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58896 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58896 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58896 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144678 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 144678 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92705 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92705 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29814 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29814 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4898 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4898 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23697 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23697 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 237383 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 237383 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267197 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267197 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14423 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26179 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2254716500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2254716500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2475419500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2475419500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 516532000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 516532000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86654500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86654500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533644500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533644500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 598000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 598000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4730136000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4730136000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5246668000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5246668000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2493280000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2493280000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2493280000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2493280000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013042 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013042 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013398 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013398 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.366441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.366441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248282 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248282 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013179 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013179 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014767 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014767 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15584.377030 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15584.377030 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26702.114233 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26702.114233 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17325.149259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks +system.cpu1.dcache.writebacks::total 197406 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19926.178370 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19926.178370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19635.953996 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19635.953996 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172868.335298 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172868.335298 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.695939 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95239.695939 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 951926 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.186802 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38745002 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 952438 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.679815 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73025806000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.186802 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974974 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974974 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 951563 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80347318 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80347318 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38745002 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38745002 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38745002 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38745002 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38745002 # number of overall hits -system.cpu1.icache.overall_hits::total 38745002 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 952438 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 952438 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 952438 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 952438 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 952438 # number of overall misses -system.cpu1.icache.overall_misses::total 952438 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8816320000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8816320000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8816320000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8816320000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8816320000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8816320000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39697440 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39697440 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39697440 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39697440 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39697440 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39697440 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023992 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023992 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023992 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023992 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023992 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.581531 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.581531 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9256.581531 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9256.581531 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38753540 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38753540 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38753540 # number of overall hits +system.cpu1.icache.overall_hits::total 38753540 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 952075 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 952075 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 952075 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 952075 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 952075 # number of overall misses +system.cpu1.icache.overall_misses::total 952075 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8812564500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8812564500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8812564500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 951926 # number of writebacks -system.cpu1.icache.writebacks::total 951926 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952438 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 952438 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 952438 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 952438 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 952438 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 952438 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks +system.cpu1.icache.writebacks::total 951563 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 952075 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 952075 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 952075 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 952075 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 952075 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8340101000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8340101000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8340101000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8340101000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8340101000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8340101000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11130500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11130500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11130500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 11130500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023992 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023992 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.581531 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99379.464286 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99379.464286 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 201450 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 201482 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8336527000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8336527000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8336527000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8336527000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8336527000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8336527000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10996500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10996500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 57990 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53299 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14769.496108 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1064390 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 67600 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.745414 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 53261 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.648393 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.118214 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 333.751919 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878722 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002359 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.020371 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.901459 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 279 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 41 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13981 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 194 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1305 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7821 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4855 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017029 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002502 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.853333 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 39716759 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 39716759 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29141 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3302 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 32443 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 117742 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 117742 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1011389 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1011389 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27835 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27835 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916991 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 916991 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103815 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 103815 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29141 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3302 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 916991 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 131650 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1081084 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29141 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3302 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 916991 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 131650 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1081084 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 285 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30019 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 30019 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23697 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23697 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34851 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34851 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35447 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 35447 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75575 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 75575 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 285 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 35447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 110426 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 146862 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 285 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 35447 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 110426 # number of overall misses -system.cpu1.l2cache.overall_misses::total 146862 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 18655500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5724000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 24379500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14027500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 14027500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17693000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17693000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 577000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 577000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1507211500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1507211500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359433500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359433500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1899319493 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1899319493 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 18655500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5724000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359433500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3406530993 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4790343993 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 18655500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5724000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359433500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3406530993 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4790343993 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29845 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3587 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 33432 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117742 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 117742 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 1011389 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 1011389 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30019 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30019 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23697 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23697 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62686 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62686 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952438 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 952438 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179390 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 179390 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29845 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3587 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 952438 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 242076 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1227946 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29845 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3587 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 952438 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 242076 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1227946 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079454 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.029582 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.848755 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 39696628 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 39696628 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28743 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3180 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 31923 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 117832 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 117832 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 1010940 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 1010940 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28052 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 28052 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916446 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 916446 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103629 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 103629 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28743 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3180 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 916446 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 131681 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1080050 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28743 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3180 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 916446 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 131681 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1080050 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30054 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 30054 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23668 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23668 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34968 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34968 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35629 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 35629 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75478 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 75478 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 35629 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 110446 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 147023 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 35629 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 110446 # number of overall misses +system.cpu1.l2cache.overall_misses::total 147023 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15962500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5289000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 21251500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13859000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 13859000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17603500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17603500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 622000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 622000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1509066000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1509066000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359934000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359934000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1890312995 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1890312995 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15962500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5289000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359934000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3399378995 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4780564495 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15962500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5289000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359934000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3399378995 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4780564495 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29425 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3446 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 32871 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117832 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 117832 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 1010940 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 1010940 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30054 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30054 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63020 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63020 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952075 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 952075 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179107 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 179107 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29425 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3446 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 952075 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 242127 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1227073 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29425 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3446 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 952075 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 242127 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1227073 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077191 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.028840 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555961 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555961 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037217 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037217 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421289 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421289 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079454 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037217 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456163 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.119600 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079454 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037217 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456163 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.119600 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20084.210526 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24650.657230 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 467.287385 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 467.287385 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.634595 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.634595 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43247.295630 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43247.295630 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38351.158067 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38351.158067 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25131.584426 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25131.584426 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20084.210526 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38351.158067 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30848.993833 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32617.995077 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20084.210526 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38351.158067 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30848.993833 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32617.995077 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554871 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554871 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037422 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037422 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421413 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421413 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077191 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037422 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456149 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.119816 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077191 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037422 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456149 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.119816 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19883.458647 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22417.194093 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.136621 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.136621 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 743.767957 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 743.767957 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43155.628003 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43155.628003 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38169.300289 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38169.300289 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25044.555963 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25044.555963 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 32515.759405 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 32515.759405 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 874 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 36491 # number of writebacks -system.cpu1.l2cache.writebacks::total 36491 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 204 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 204 # number of ReadExReq MSHR hits +system.cpu1.l2cache.unused_prefetches 862 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 36438 # number of writebacks +system.cpu1.l2cache.writebacks::total 36438 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 196 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 196 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 78 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 78 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 87 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 87 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 282 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 305 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 282 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 305 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 701 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 283 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26312 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 26312 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30019 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30019 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23697 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23697 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34647 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34647 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35429 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35429 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75497 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75497 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 701 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 283 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35429 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110144 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 146557 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 701 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 283 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35429 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110144 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26312 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 172869 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 302 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 681 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 947 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 26287 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30054 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30054 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23668 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23668 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34772 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34772 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35611 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35611 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75391 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75391 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 681 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35611 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110163 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 146721 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 681 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35611 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110163 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 173008 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14535 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26291 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3995000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 18386500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 996240965 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 460605000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 460605000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354483500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354483500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 493000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 493000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1271760500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1271760500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1146491500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1146491500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1443582493 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1443582493 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3995000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1146491500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2715342993 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3880220993 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3995000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1146491500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2715342993 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4876461958 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10234500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377871000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2388105500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10234500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377871000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2388105500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029433 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26293 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3693000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 965321170 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 461957500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 461957500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354728500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1277222000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1145765500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1145765500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1434909495 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1434909495 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3693000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1145765500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712131495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552707 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552707 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420854 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420854 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119351 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140779 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2407842 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1213344 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118526 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110630 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7896 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 52421 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1221670 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 155519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1031415 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 35412 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31701 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73485 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69767 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67286 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295145 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 55 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2857026 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915642 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8405 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62913 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3843986 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121886464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30908928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119380 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152929120 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 368607 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5126040 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1602092 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.097939 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1453081 90.70% 90.70% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141115 8.81% 99.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 7896 0.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1602092 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2385821492 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79306117 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1428899351 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412338887 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4820495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33080974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2330,58 +2337,58 @@ system.iobus.pkt_size_system.bridge.master::total 162796 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48391001 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6378000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38950500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187782564 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.472132 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272036828000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472132 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -2389,7 +2396,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2398,14 +2405,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33219876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33219876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4376166688 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4376166688 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4409386564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4409386564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4409386564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4409386564 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2422,19 +2429,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130274.023529 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120874.655665 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120874.655665 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -2446,14 +2453,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20469876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20469876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562591001 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2562591001 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2583060877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2583060877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2583060877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2583060877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2462,591 +2469,587 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80274.023529 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80274.023529 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70742.905284 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70742.905284 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 145308 # number of replacements -system.l2c.tags.tagsinuse 65153.014694 # Cycle average of tags in use -system.l2c.tags.total_refs 608197 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 210799 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.885199 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94570968000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6725.818981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 88.835717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.039308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8741.022578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6775.934473 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.618119 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2235.319135 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3466.513349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2242.708901 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.102628 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.133377 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.103393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.531986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.034108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052895 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994156 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31590 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33841 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4772 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26692 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1899 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31836 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.482025 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.516373 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6845829 # Number of tag accesses -system.l2c.tags.data_accesses 6845829 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269041 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269041 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 43018 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5569 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48587 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2756 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2348 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4245 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1488 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5733 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 501 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 88 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 68822 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 63059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47426 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 132 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 22 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 31931 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 13672 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5861 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 231514 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 501 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 88 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 68822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 67304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47426 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 22 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 31931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 15160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5861 # number of demand (read+write) hits -system.l2c.demand_hits::total 237247 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 501 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 88 # number of overall hits -system.l2c.overall_hits::cpu0.inst 68822 # number of overall hits -system.l2c.overall_hits::cpu0.data 67304 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47426 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 132 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 22 # number of overall hits -system.l2c.overall_hits::cpu1.inst 31931 # number of overall hits -system.l2c.overall_hits::cpu1.data 15160 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5861 # number of overall hits -system.l2c.overall_hits::total 237247 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 567 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 233 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 800 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 71 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 57 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 128 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8671 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20001 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 149 # number of ReadSharedReq misses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 144965 # number of replacements +system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use +system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6850011 # Number of tag accesses +system.l2c.tags.data_accesses 6850011 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 63546 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47286 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 133 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 32119 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 13663 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5831 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 232111 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 596 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 68829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 67825 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47286 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 32119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 15185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5831 # number of demand (read+write) hits +system.l2c.demand_hits::total 237912 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 596 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits +system.l2c.overall_hits::cpu0.inst 68829 # number of overall hits +system.l2c.overall_hits::cpu0.data 67825 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47286 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 133 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits +system.l2c.overall_hits::cpu1.inst 32119 # number of overall hits +system.l2c.overall_hits::cpu1.data 15185 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5831 # number of overall hits +system.l2c.overall_hits::total 237912 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 404 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 229 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 633 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 106 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 82 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 188 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11300 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8634 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19934 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 147 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 22928 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 10009 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132762 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 16 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 3498 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1729 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6519 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 177611 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 149 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 22922 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9947 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 19 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 3492 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1704 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 177568 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 147 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22928 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 132762 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3498 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10400 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6519 # number of demand (read+write) misses -system.l2c.demand_misses::total 197612 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 149 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22922 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 21247 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3492 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10338 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) misses +system.l2c.demand_misses::total 197502 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 147 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22928 # number of overall misses -system.l2c.overall_misses::cpu0.data 21339 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 132762 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3498 # number of overall misses -system.l2c.overall_misses::cpu1.data 10400 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6519 # number of overall misses -system.l2c.overall_misses::total 197612 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 7996500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 709500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 8706000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 618000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 99500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 717500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1582862000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 826941000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2409803000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 24166000 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu0.inst 22922 # number of overall misses +system.l2c.overall_misses::cpu0.data 21247 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 132993 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3492 # number of overall misses +system.l2c.overall_misses::cpu1.data 10338 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6343 # number of overall misses +system.l2c.overall_misses::total 197502 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 7730000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 962500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 8692500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 689500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 165500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 855000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1562017000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 830214000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2392231000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21395500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2324658500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1196554000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3966500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 386401500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 279812500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 21063610044 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 24166000 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2310573000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1198855000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1721000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 383378500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 272430000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 20918670107 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 21395500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2324658500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2779416000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 3966500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 386401500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1106753500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 23473413044 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 24166000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2310573000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2760872000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1721000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 383378500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1102644000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 23310901107 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 21395500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2324658500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2779416000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 3966500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 386401500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1106753500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of overall miss cycles -system.l2c.overall_miss_latency::total 23473413044 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 269041 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 269041 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 43585 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5802 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 49387 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2827 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2405 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5232 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15575 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10159 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25734 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 650 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 89 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 91750 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 73068 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180188 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 148 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 22 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 35429 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 15401 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12380 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 409125 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 650 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 89 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 91750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 88643 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 148 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 35429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25560 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12380 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 434859 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 650 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 89 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 91750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 88643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 148 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 35429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25560 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12380 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 434859 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.013009 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.040159 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.016199 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.025115 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.023701 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.024465 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.727448 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.853529 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.777221 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011236 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249896 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.136982 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098733 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.112265 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.434124 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.011236 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.249896 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.240730 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.098733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.406886 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.454428 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.011236 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.249896 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.240730 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.098733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.406886 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.454428 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14103.174603 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3045.064378 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 10882.500000 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8704.225352 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1745.614035 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5605.468750 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139705.383936 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95368.584938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 120484.125794 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 2310573000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2760872000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1721000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 383378500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1102644000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of overall miss cycles +system.l2c.overall_miss_latency::total 23310901107 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 269158 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 269158 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 43332 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5851 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 49183 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2849 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2387 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 5236 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15579 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10156 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25735 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 743 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 97 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 91751 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 73493 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180279 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 152 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 35611 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 15367 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12174 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 409679 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 743 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 97 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 91751 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 89072 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180279 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 152 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 35611 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25523 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12174 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 435414 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 743 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 97 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 91751 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 89072 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180279 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 152 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 35611 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25523 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12174 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 435414 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.009323 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.039139 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.012870 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037206 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034353 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.035905 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.725335 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.850138 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.774587 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010309 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249828 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.135346 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098060 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110887 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.433432 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.010309 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.249828 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.238537 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.098060 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.405046 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.453596 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.010309 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.249828 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.238537 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.098060 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.405046 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.453596 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19133.663366 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4203.056769 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13732.227488 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6504.716981 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2018.292683 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4547.872340 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138231.592920 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96156.358582 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 120007.574997 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101389.501919 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 119547.806974 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110463.550600 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 161834.875651 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 118594.062552 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 100801.544368 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 120524.278677 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109787.657503 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 159876.760563 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 117806.531059 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 101389.501919 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 130250.527204 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 110463.550600 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 106418.605769 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 118785.362448 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 118028.683796 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 101389.501919 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 130250.527204 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 110463.550600 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 106418.605769 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 118785.362448 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 118028.683796 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 151 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 4 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 105581 # number of writebacks -system.l2c.writebacks::total 105581 # number of writebacks +system.l2c.writebacks::writebacks 105386 # number of writebacks +system.l2c.writebacks::total 105386 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4797 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4797 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 567 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 233 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 800 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 71 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 57 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 128 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11330 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8671 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 20001 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 149 # number of ReadSharedReq MSHR misses +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 4794 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 4794 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 404 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 229 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 106 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 82 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 188 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11300 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8634 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19934 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 147 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22925 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 10009 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3494 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1729 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 177604 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 149 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22919 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9947 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3492 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1704 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 177565 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 147 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 22925 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 21339 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3494 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10400 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 197605 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 149 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 22919 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 21247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3492 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 197499 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 147 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 22925 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 21339 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3494 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10400 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 197605 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 22919 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 21247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3492 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 197499 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14420 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38386 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38391 # number of ReadReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31026 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31027 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26176 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69412 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13077000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4990500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 18067500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1886000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1373500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 3259500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1469562000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 740230501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2209792501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26178 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69418 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 8946500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5034000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 13980500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2786000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1998500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4784500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1449017000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743874000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2192891000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2094658500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1096464000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 351259500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 262522001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19286615050 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2081229000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1099385000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 348458500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 255390000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19142863612 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2094658500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2566026000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 351259500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1002752502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21496407551 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2081229000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2548402000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 348458500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 999264000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21335754612 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2094658500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2566026000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 351259500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1002752502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21496407551 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2081229000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2548402000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 348458500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 999264000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21335754612 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4071417000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7882500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2118238500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6426386500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4072237500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2117933000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6426767500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4071417000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7882500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2118238500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6426386500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4072237500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7748500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2117933000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6426767500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.013009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.040159 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.016199 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.025115 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.023701 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.024465 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727448 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.777221 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.136982 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.112265 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.434107 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.454412 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.454412 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23063.492063 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21418.454936 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22584.375000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26563.380282 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24096.491228 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25464.843750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129705.383936 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85368.527390 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 110484.100845 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.009323 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.039139 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.012870 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034353 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035905 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725335 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850138 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774587 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.135346 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110887 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.433425 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.453589 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.453589 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22144.801980 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 519453 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 291586 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38386 # Transaction distribution -system.membus.trans_dist::ReadResp 216245 # Transaction distribution -system.membus.trans_dist::WriteReq 31026 # Transaction distribution -system.membus.trans_dist::WriteResp 31026 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141787 # Transaction distribution -system.membus.trans_dist::CleanEvict 20009 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38952 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38391 # Transaction distribution +system.membus.trans_dist::ReadResp 216211 # Transaction distribution +system.membus.trans_dist::WriteReq 31027 # Transaction distribution +system.membus.trans_dist::WriteResp 31027 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution +system.membus.trans_dist::CleanEvict 19995 # Transaction distribution +system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40468 # Transaction distribution -system.membus.trans_dist::ReadExResp 19978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177859 # Transaction distribution +system.membus.trans_dist::ReadExReq 40431 # Transaction distribution +system.membus.trans_dist::ReadExResp 19912 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14184 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19616228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19808736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22126880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123082 # Total snoops (count) +system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 127509 # Total snoops (count) system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426925 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011573 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106956 # Request fanout histogram +system.membus.snoop_fanout::samples 426843 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421984 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 4941 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426925 # Request fanout histogram -system.membus.reqLayer0.occupancy 95052999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426843 # Request fanout histogram +system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12480499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1015492813 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1151697269 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1408128 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3078,77 +3081,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1122951 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 592347 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 209143 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29689 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 28433 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1256 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38389 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 568851 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31026 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31026 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 374622 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 155080 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 112572 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44056 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 156628 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51647 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51647 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 530464 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4356 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1342563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1751440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38341228 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7151796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45493024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 399228 # Total snoops (count) -system.toL2Bus.snoopTraffic 16183244 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 957878 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.406657 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493872 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 402215 # Total snoops (count) +system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 569606 59.47% 59.47% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 387016 40.40% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1256 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 957878 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 953761642 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 722683237 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286574903 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 9c3703a65..a1ac44f79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.854926 # Number of seconds simulated -sim_ticks 2854925996500 # Number of ticks simulated -final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.854886 # Number of seconds simulated +sim_ticks 2854886132500 # Number of ticks simulated +final_tick 2854886132500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259837 # Simulator instruction rate (inst/s) -host_op_rate 314167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6622138542 # Simulator tick rate (ticks/s) -host_mem_usage 588096 # Number of bytes of host memory used -host_seconds 431.12 # Real time elapsed on the host -sim_insts 112020669 # Number of instructions simulated -sim_ops 135443008 # Number of ops (including micro ops) simulated +host_inst_rate 259825 # Simulator instruction rate (inst/s) +host_op_rate 314145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6635713455 # Simulator tick rate (ticks/s) +host_mem_usage 588360 # Number of bytes of host memory used +host_seconds 430.23 # Real time elapsed on the host +sim_insts 111784531 # Number of instructions simulated +sim_ops 135154718 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1667200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9190572 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 7232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1667840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9176172 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10865900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1667200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1667200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7979712 # Number of bytes written to this memory +system.physmem.bytes_read::total 10852268 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1667840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1667840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7959296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7997236 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 110 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144124 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7976820 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 113 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170301 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124683 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170088 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124364 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129064 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 583973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3219198 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128745 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 584205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3214199 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3806018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 583973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 583973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2795068 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3801296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 584205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 584205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2787956 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2801206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2795068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 583973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3225336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2794094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2787956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 584205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3220337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6607224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170301 # Number of read requests accepted -system.physmem.writeReqs 129064 # Number of write requests accepted -system.physmem.readBursts 170301 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129064 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10890496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 8010048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10865900 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7997236 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6595390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170088 # Number of read requests accepted +system.physmem.writeReqs 128745 # Number of write requests accepted +system.physmem.readBursts 170088 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128745 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10876160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 7989120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10852268 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7976820 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10638 # Per bank write bursts -system.physmem.perBankRdBursts::1 10529 # Per bank write bursts -system.physmem.perBankRdBursts::2 10665 # Per bank write bursts -system.physmem.perBankRdBursts::3 10242 # Per bank write bursts -system.physmem.perBankRdBursts::4 13390 # Per bank write bursts -system.physmem.perBankRdBursts::5 10196 # Per bank write bursts -system.physmem.perBankRdBursts::6 10392 # Per bank write bursts -system.physmem.perBankRdBursts::7 10920 # Per bank write bursts -system.physmem.perBankRdBursts::8 10199 # Per bank write bursts -system.physmem.perBankRdBursts::9 10416 # Per bank write bursts -system.physmem.perBankRdBursts::10 10277 # Per bank write bursts -system.physmem.perBankRdBursts::11 9652 # Per bank write bursts -system.physmem.perBankRdBursts::12 10777 # Per bank write bursts -system.physmem.perBankRdBursts::13 11476 # Per bank write bursts -system.physmem.perBankRdBursts::14 10256 # Per bank write bursts -system.physmem.perBankRdBursts::15 10139 # Per bank write bursts -system.physmem.perBankWrBursts::0 7926 # Per bank write bursts -system.physmem.perBankWrBursts::1 7916 # Per bank write bursts -system.physmem.perBankWrBursts::2 8341 # Per bank write bursts -system.physmem.perBankWrBursts::3 7830 # Per bank write bursts -system.physmem.perBankWrBursts::4 7635 # Per bank write bursts -system.physmem.perBankWrBursts::5 7427 # Per bank write bursts -system.physmem.perBankWrBursts::6 7524 # Per bank write bursts -system.physmem.perBankWrBursts::7 8090 # Per bank write bursts -system.physmem.perBankWrBursts::8 7812 # Per bank write bursts -system.physmem.perBankWrBursts::9 7846 # Per bank write bursts -system.physmem.perBankWrBursts::10 7622 # Per bank write bursts -system.physmem.perBankWrBursts::11 7450 # Per bank write bursts -system.physmem.perBankWrBursts::12 8154 # Per bank write bursts -system.physmem.perBankWrBursts::13 8593 # Per bank write bursts -system.physmem.perBankWrBursts::14 7575 # Per bank write bursts -system.physmem.perBankWrBursts::15 7416 # Per bank write bursts +system.physmem.perBankRdBursts::0 10602 # Per bank write bursts +system.physmem.perBankRdBursts::1 10348 # Per bank write bursts +system.physmem.perBankRdBursts::2 10682 # Per bank write bursts +system.physmem.perBankRdBursts::3 10189 # Per bank write bursts +system.physmem.perBankRdBursts::4 13369 # Per bank write bursts +system.physmem.perBankRdBursts::5 10294 # Per bank write bursts +system.physmem.perBankRdBursts::6 10368 # Per bank write bursts +system.physmem.perBankRdBursts::7 10838 # Per bank write bursts +system.physmem.perBankRdBursts::8 10130 # Per bank write bursts +system.physmem.perBankRdBursts::9 10489 # Per bank write bursts +system.physmem.perBankRdBursts::10 10055 # Per bank write bursts +system.physmem.perBankRdBursts::11 9592 # Per bank write bursts +system.physmem.perBankRdBursts::12 10755 # Per bank write bursts +system.physmem.perBankRdBursts::13 11804 # Per bank write bursts +system.physmem.perBankRdBursts::14 10513 # Per bank write bursts +system.physmem.perBankRdBursts::15 9912 # Per bank write bursts +system.physmem.perBankWrBursts::0 7846 # Per bank write bursts +system.physmem.perBankWrBursts::1 7741 # Per bank write bursts +system.physmem.perBankWrBursts::2 8334 # Per bank write bursts +system.physmem.perBankWrBursts::3 7790 # Per bank write bursts +system.physmem.perBankWrBursts::4 7606 # Per bank write bursts +system.physmem.perBankWrBursts::5 7522 # Per bank write bursts +system.physmem.perBankWrBursts::6 7517 # Per bank write bursts +system.physmem.perBankWrBursts::7 7997 # Per bank write bursts +system.physmem.perBankWrBursts::8 7756 # Per bank write bursts +system.physmem.perBankWrBursts::9 7896 # Per bank write bursts +system.physmem.perBankWrBursts::10 7435 # Per bank write bursts +system.physmem.perBankWrBursts::11 7391 # Per bank write bursts +system.physmem.perBankWrBursts::12 8149 # Per bank write bursts +system.physmem.perBankWrBursts::13 8812 # Per bank write bursts +system.physmem.perBankWrBursts::14 7798 # Per bank write bursts +system.physmem.perBankWrBursts::15 7240 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 2854925546000 # Total gap between requests +system.physmem.numWrRetry 69 # Number of times write queue was full causing retry +system.physmem.totGap 2854885682000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169744 # Read request sizes (log2) +system.physmem.readPktSize::6 169531 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 160221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124364 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 160094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,178 +160,176 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 138 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.849340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.889118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.883375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21657 35.85% 35.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14616 24.19% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6864 11.36% 71.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3516 5.82% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2636 4.36% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1611 2.67% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1067 1.77% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 953 1.58% 87.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7494 12.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60414 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.463041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 582.417033 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6195 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.612325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.506399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.136235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21716 35.99% 35.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14599 24.19% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6802 11.27% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3528 5.85% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2551 4.23% 81.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1581 2.62% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1111 1.84% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1010 1.67% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7449 12.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6172 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.532242 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 583.546907 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6171 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.199645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.300177 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.412164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5485 88.52% 88.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 67 1.08% 89.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.69% 90.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 35 0.56% 90.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 272 4.39% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 29 0.47% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 8 0.13% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.18% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.18% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.11% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 2.23% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.11% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.10% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 13 0.21% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.19% 99.48% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6172 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.225211 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.326492 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.268498 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5463 88.51% 88.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 63 1.02% 89.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.53% 90.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 41 0.66% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 274 4.44% 95.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 26 0.42% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.23% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.13% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.16% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 140 2.27% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.10% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.18% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.23% 99.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads -system.physmem.totQLat 4595967000 # Total ticks spent queuing -system.physmem.totMemAccLat 7786542000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27009.04 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::140-143 6 0.10% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6172 # Writes before turning the bus around for reads +system.physmem.totQLat 4562123250 # Total ticks spent queuing +system.physmem.totMemAccLat 7748498250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849700000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26845.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45759.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45595.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing -system.physmem.readRowHits 140583 # Number of row buffer hits during reads -system.physmem.writeRowHits 94323 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.35 # Row buffer hit rate for writes -system.physmem.avgGap 9536604.30 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 218405460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 116085255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 620980080 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 327236580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6016710960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4587085260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 376629120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12457025670 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8414413920 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 671932680540 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 705069857835 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.966071 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2843548486750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 708499000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2558586000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2794649429000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21912527500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7778804250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 27318150750 # Time in different power states -system.physmem_1.actEnergy 212957640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113185875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 593990880 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 326082960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6113824080.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4455367380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 374460480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12365716800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8661645120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 671979444945 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 705199696980 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.011550 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2844173514000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 705782750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2600572000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2794499397250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22556418250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7446062750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 27117763500 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing +system.physmem.readRowHits 140395 # Number of row buffer hits during reads +system.physmem.writeRowHits 94027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.31 # Row buffer hit rate for writes +system.physmem.avgGap 9553448.52 # Average gap between requests +system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 217784280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115755090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 618966600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 325482660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6028389120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4546972650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 380659200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12537712590 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8446773120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 671876398965 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 705097688865 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.979269 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2843583812750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 720868250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2563490000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2794425375000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21996678750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7684667500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 27495053000 # Time in different power states +system.physmem_1.actEnergy 213100440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113261775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 594405000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 326129940 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6103375200.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4480349340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 365416320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12364122510 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8637319200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 671971041390 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 705171178185 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.005010 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2844103138750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 682770250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2596086000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2794495958000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22493040000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7504072000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 27114206250 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -344,30 +342,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31074836 # Number of BP lookups -system.cpu.branchPred.condPredicted 16867509 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2481345 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18655029 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10408802 # Number of BTB hits +system.cpu.branchPred.lookups 31050902 # Number of BP lookups +system.cpu.branchPred.condPredicted 16823011 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2467385 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18598277 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10398347 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.796225 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7856601 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1514233 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3068747 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2872226 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 196521 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 109392 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.910271 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7909634 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1502216 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3035557 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2846976 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 188581 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109207 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,58 +395,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 68070 # Table walker walks requested -system.cpu.dtb.walker.walksShort 68070 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44787 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23283 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 68070 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 68070 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 68070 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7877 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8445.879455 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 9567.630419 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 7869 99.90% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 67916 # Table walker walks requested +system.cpu.dtb.walker.walksShort 67916 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44853 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23063 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 67916 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 67916 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 67916 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8470.700593 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9365.136659 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7877 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7871 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6513 82.68% 82.68% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1364 17.32% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7877 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68070 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6482 82.35% 82.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1389 17.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7871 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67916 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68070 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67916 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7877 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 75947 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75787 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24743648 # DTB read hits -system.cpu.dtb.read_misses 61017 # DTB read misses -system.cpu.dtb.write_hits 19435570 # DTB write hits -system.cpu.dtb.write_misses 7053 # DTB write misses +system.cpu.dtb.read_hits 24685993 # DTB read hits +system.cpu.dtb.read_misses 61030 # DTB read misses +system.cpu.dtb.write_hits 19409907 # DTB write hits +system.cpu.dtb.write_misses 6886 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4276 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1444 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1826 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24804665 # DTB read accesses -system.cpu.dtb.write_accesses 19442623 # DTB write accesses +system.cpu.dtb.read_accesses 24747023 # DTB read accesses +system.cpu.dtb.write_accesses 19416793 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44179218 # DTB hits -system.cpu.dtb.misses 68070 # DTB misses -system.cpu.dtb.accesses 44247288 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44095900 # DTB hits +system.cpu.dtb.misses 67916 # DTB misses +system.cpu.dtb.accesses 44163816 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -478,39 +475,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5855 # Table walker walks requested -system.cpu.itb.walker.walksShort 5855 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 322 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5533 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5855 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5855 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5855 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3194 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10424.389480 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8603.860466 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 6932.586443 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.80% 57.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 798 24.98% 82.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 544 17.03% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5836 # Table walker walks requested +system.cpu.itb.walker.walksShort 5836 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 323 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5513 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5836 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5836 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5836 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3199 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10502.500781 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8663.235820 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 6980.719897 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.67% 57.67% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 784 24.51% 82.18% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 564 17.63% 99.81% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3194 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3199 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2884 90.29% 90.29% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3194 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2889 90.31% 90.31% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.69% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3199 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5855 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5855 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5836 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5836 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3194 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3194 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57481594 # ITB inst hits -system.cpu.itb.inst_misses 5855 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3199 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3199 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9035 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57468050 # ITB inst hits +system.cpu.itb.inst_misses 5836 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -519,21 +516,21 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2915 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2922 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8308 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57487449 # ITB inst accesses -system.cpu.itb.hits 57481594 # DTB hits -system.cpu.itb.misses 5855 # DTB misses -system.cpu.itb.accesses 57487449 # DTB accesses +system.cpu.itb.inst_accesses 57473886 # ITB inst accesses +system.cpu.itb.hits 57468050 # DTB hits +system.cpu.itb.misses 5836 # DTB misses +system.cpu.itb.accesses 57473886 # DTB accesses system.cpu.numPwrStateTransitions 6066 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887934091.386746 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17437787888.707882 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887944293.276624 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17437791477.805088 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -541,560 +538,561 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499966196768 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966835544 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 161821897324 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 323646748 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 161751090992 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 323505132 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112020669 # Number of instructions committed -system.cpu.committedOps 135443008 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7814596 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111784531 # Number of instructions committed +system.cpu.committedOps 135154718 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7776689 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5386269471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.889170 # CPI: cycles per instruction -system.cpu.ipc 0.346120 # IPC: instructions per cycle +system.cpu.quiesceCycles 5386331427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.894006 # CPI: cycles per instruction +system.cpu.ipc 0.345542 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90804901 67.04% 67.04% # Class of committed instruction -system.cpu.op_class_0::IntMult 113201 0.08% 67.13% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::MemRead 24247912 17.90% 85.04% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20254880 14.95% 99.99% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90595549 67.03% 67.03% # Class of committed instruction +system.cpu.op_class_0::IntMult 113150 0.08% 67.12% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8471 0.01% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::MemRead 24195627 17.90% 85.02% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20228352 14.97% 99.99% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135443008 # Class of committed instruction +system.cpu.op_class_0::total 135154718 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 217947056 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105699692 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 844723 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.945160 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637807 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 845235 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.444914 # Average number of references to valid blocks. +system.cpu.tickCycles 217865051 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105640081 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 843791 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.945118 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42554576 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844303 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.402019 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.945160 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.945118 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 364 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176206878 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176206878 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23101260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23101260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18273431 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18273431 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356861 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356861 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443340 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443340 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460050 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460050 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41374691 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41374691 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41731552 # number of overall hits -system.cpu.dcache.overall_hits::total 41731552 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 465078 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 465078 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548776 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548776 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169103 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169103 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22503 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22503 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175868835 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175868835 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23043762 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23043762 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18247268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18247268 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 357174 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 357174 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443432 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443432 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460038 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460038 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41291030 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41291030 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41648204 # number of overall hits +system.cpu.dcache.overall_hits::total 41648204 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 465012 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 465012 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548381 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548381 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 168658 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 168658 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22398 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22398 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1013854 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013854 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1182957 # number of overall misses -system.cpu.dcache.overall_misses::total 1182957 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7334484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7334484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26875060480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26875060480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306737000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306737000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1013393 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013393 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1182051 # number of overall misses +system.cpu.dcache.overall_misses::total 1182051 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7327923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7327923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26756956980 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26756956980 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306920500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306920500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34209544480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34209544480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34209544480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34209544480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23566338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23566338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18822207 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18822207 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 525964 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 525964 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465843 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465843 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460052 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460052 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42388545 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42388545 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42914509 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42914509 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.019735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029156 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029156 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321511 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.321511 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048306 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048306 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 34084879980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34084879980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34084879980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34084879980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23508774 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23508774 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18795649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18795649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 525832 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 525832 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465830 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465830 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460040 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460040 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42304423 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42304423 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42830255 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42830255 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019780 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029176 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029176 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.320745 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.320745 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048082 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023918 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023918 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027565 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027565 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023955 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023955 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027599 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027599 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33742.081680 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28918.671160 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 224 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33634.414270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28835.371723 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.571429 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 702249 # number of writebacks -system.cpu.dcache.writebacks::total 702249 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45641 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45641 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249535 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249535 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 295176 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 295176 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 295176 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 295176 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419437 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 419437 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299241 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299241 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121149 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121149 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8225 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8225 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 701301 # number of writebacks +system.cpu.dcache.writebacks::total 701301 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45802 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45802 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249489 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249489 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14157 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14157 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 295291 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 295291 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 295291 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 295291 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 419210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298892 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298892 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 120813 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 120813 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8241 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8241 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 718678 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 718678 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 839827 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 839827 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 718102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 718102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 838915 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 838915 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14303453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14303453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1653166500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1653166500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 121747500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121747500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14235579000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14235579000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1652909500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1652909500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 122323000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 122323000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20751294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20751294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22404460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22404460500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305636000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305636000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017798 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017798 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230337 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230337 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20674320500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20674320500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22327230000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22327230000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305432000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305432000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305432000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305432000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015902 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229756 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229756 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016955 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016955 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019570 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019570 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016975 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019587 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019587 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2891615 # number of replacements -system.cpu.icache.tags.tagsinuse 511.370867 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54580851 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2892127 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.872218 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 16116545500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.370867 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2889413 # number of replacements +system.cpu.icache.tags.tagsinuse 511.370681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54569461 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2889925 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.882656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16116553500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.370681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60365128 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60365128 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54580851 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54580851 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54580851 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54580851 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54580851 # number of overall hits -system.cpu.icache.overall_hits::total 54580851 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2892139 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2892139 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2892139 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2892139 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2892139 # number of overall misses -system.cpu.icache.overall_misses::total 2892139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39804335500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39804335500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39804335500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39804335500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39804335500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39804335500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57472990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57472990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57472990 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57472990 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57472990 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57472990 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050322 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050322 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050322 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050322 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050322 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050322 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13762.939990 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13762.939990 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60349332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60349332 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 54569461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54569461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54569461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54569461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54569461 # number of overall hits +system.cpu.icache.overall_hits::total 54569461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2889936 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2889936 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2889936 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2889936 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2889936 # number of overall misses +system.cpu.icache.overall_misses::total 2889936 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39799359500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39799359500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39799359500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39799359500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39799359500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39799359500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57459397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57459397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57459397 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57459397 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57459397 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57459397 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050295 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050295 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050295 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050295 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050295 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050295 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.709650 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13771.709650 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13771.709650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13771.709650 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2891615 # number of writebacks -system.cpu.icache.writebacks::total 2891615 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2892139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2892139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2892139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2892139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2892139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2892139 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 2889413 # number of writebacks +system.cpu.icache.writebacks::total 2889413 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889936 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2889936 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2889936 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2889936 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2889936 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2889936 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36912197500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36912197500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36912197500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36912197500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36912197500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36912197500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36909424500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36909424500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36909424500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36909424500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36909424500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36909424500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050322 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050322 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050322 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050295 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050295 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050295 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12771.709996 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12771.709996 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 97098 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65145.315179 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7321379 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162490 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 45.057413 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 271905816000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 69.248317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032949 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.808069 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994039 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4586 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60692 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997040 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 60089878 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 60089878 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68391 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3372 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71763 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 702249 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 702249 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2840964 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2840964 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2784 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 166689 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 166689 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2869145 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2869145 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534458 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 534458 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 68391 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3372 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2869145 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 701147 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3642055 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 68391 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3372 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2869145 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 701147 # number of overall hits -system.cpu.l2cache.overall_hits::total 3642055 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 110 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 96873 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65145.709178 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7314750 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 45.076259 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 99924187000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 73.512854 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023684 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184798 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.808125 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65344 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4564 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60694 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 60034528 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 60034528 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3361 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71164 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 701301 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 701301 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2838672 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2838672 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2815 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2815 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 166503 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 166503 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866935 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2866935 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533944 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 533944 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 67803 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3361 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2866935 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 700447 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3638546 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3361 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2866935 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 700447 # number of overall hits +system.cpu.l2cache.overall_hits::total 3638546 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 113 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 114 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 129768 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 129768 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22956 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 22956 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14347 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 14347 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 110 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 22956 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144115 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 167183 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 110 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 22956 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144115 # number of overall misses -system.cpu.l2cache.overall_misses::total 167183 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35753500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 35946500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 129573 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 129573 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 22965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14315 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14315 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 113 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 22965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143888 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166967 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 113 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 22965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143888 # number of overall misses +system.cpu.l2cache.overall_misses::total 166967 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 38662500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 89500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 38752000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 174000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12066822500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12066822500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2380927500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2380927500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1746972000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1746972000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35753500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2380927500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13813794500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16230668500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35753500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2380927500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13813794500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16230668500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68501 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3374 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 71875 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 702249 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 702249 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2840964 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2840964 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2790 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000990500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12000990500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2404531500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2404531500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1744805500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1744805500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 38662500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 89500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2404531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13745796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16189079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 38662500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 89500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2404531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13745796000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16189079500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 71278 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 701301 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 701301 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2838672 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2838672 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2821 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2892101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 2892101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68501 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3374 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2892101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 845262 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3809238 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68501 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3374 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2892101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 845262 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3809238 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001558 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296076 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296076 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889900 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2889900 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548259 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 548259 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67916 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3362 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2889900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 844335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3805513 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67916 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3362 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2889900 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 844335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3805513 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001664 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001599 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002127 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002127 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437730 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.437730 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026142 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026142 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001606 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170497 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.043889 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001606 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170497 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.043889 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437634 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.437634 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007947 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007947 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026110 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026110 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001664 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.043875 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001664 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000297 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.043875 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 342146.017699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 339929.824561 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92619.531075 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92619.531075 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104704.180274 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104704.180274 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121886.517639 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121886.517639 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96959.755521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96959.755521 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 88493 # number of writebacks -system.cpu.l2cache.writebacks::total 88493 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 14 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 145 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 145 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 145 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 145 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 159 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 110 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88174 # number of writebacks +system.cpu.l2cache.writebacks::total 88174 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 144 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 144 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 144 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 157 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 114 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129768 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 129768 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22942 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22942 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14202 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14202 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 110 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22942 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143970 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 167024 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 110 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22942 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143970 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 167024 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129573 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 129573 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22952 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22952 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 113 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22952 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143744 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166810 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 113 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22952 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143744 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166810 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable @@ -1103,145 +1101,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34653500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34826500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 37532500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37612000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10769142500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10769142500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2149471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2149471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1592398000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1592398000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34653500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2149471500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12361540500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14545838500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34653500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2149471500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12361540500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14545838500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10705260500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10705260500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2173786500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2173786500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1590255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1590255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 37532500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 79500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2173786500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12295516000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14506914500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 37532500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 79500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2173786500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12295516000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14506914500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916431500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133251000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916233500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133053000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916431500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133251000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001558 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916233500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133053000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001599 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002127 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002127 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025878 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025878 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.043847 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.043847 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437634 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437634 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007942 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025847 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025847 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.043834 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.043834 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 329929.824561 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82619.531075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82619.531075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94710.112409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94710.112409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112219.003599 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7507397 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770030 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58003 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 175 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7501348 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767098 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 136990 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578080 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3574918 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 790742 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2891615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151079 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 789475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2889413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2792 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2892139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 549026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8682092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658406 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14762 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11515114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370357376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99233193 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 274004 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469878069 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132782 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5798856 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4006498 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.022233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.147442 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 548482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8675486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2655698 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158895 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11504790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370075584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99113193 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469473889 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132758 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5779048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4002764 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.022319 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.147720 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3917420 97.78% 97.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 89078 2.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3913425 97.77% 97.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 89339 2.23% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4006498 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7428208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4002764 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7421735500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 281377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 289875 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4343459350 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4340119421 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1314433554 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1313068534 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11390994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11352493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 91384437 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 91007942 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1292,21 +1291,21 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46308000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46393500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 618500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -1326,32 +1325,32 @@ system.iobus.reqLayer20.occupancy 10000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6088500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6090000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39091500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39095500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187755828 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187683346 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033906 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033754 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272036495000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033906 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064619 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064619 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272028370000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033754 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064610 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064610 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1360,14 +1359,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 37411877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 37411877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4363182951 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4363182951 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4400594828 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4400594828 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4400594828 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4400594828 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29456377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29456377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4371874969 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4371874969 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4401331346 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4401331346 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4401331346 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4401331346 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1384,14 +1383,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 159879.816239 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120703.133140 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120703.133140 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125881.952991 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120723.334961 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120723.334961 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1408,14 +1407,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 25711877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 25711877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549871160 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2549871160 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2575583037 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2575583037 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2575583037 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2575583037 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17756377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17756377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558822831 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2558822831 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2576579208 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2576579208 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2576579208 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2576579208 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1424,90 +1423,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 337068 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 138136 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 489 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 336642 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 137901 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34249 # Transaction distribution -system.membus.trans_dist::ReadResp 71739 # Transaction distribution +system.membus.trans_dist::ReadResp 71720 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124683 # Transaction distribution -system.membus.trans_dist::CleanEvict 8839 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124364 # Transaction distribution +system.membus.trans_dist::CleanEvict 8933 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129646 # Transaction distribution -system.membus.trans_dist::ReadExResp 129646 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37490 # Transaction distribution +system.membus.trans_dist::ReadExReq 129451 # Transaction distribution +system.membus.trans_dist::ReadExResp 129451 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37471 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4363 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446194 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553762 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 627311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 626659 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16546016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16709801 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16511968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16675753 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19026921 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 505 # Total snoops (count) -system.membus.snoopTraffic 32192 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 265323 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018540 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134893 # Request fanout histogram +system.membus.pkt_size::total 18992873 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4867 # Total snoops (count) +system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 265109 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134973 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 260404 98.15% 98.15% # Request fanout histogram -system.membus.snoop_fanout::1 4919 1.85% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 260188 98.14% 98.14% # Request fanout histogram +system.membus.snoop_fanout::1 4921 1.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 265323 # Request fanout histogram -system.membus.reqLayer0.occupancy 92820000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 265109 # Request fanout histogram +system.membus.reqLayer0.occupancy 92913500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 905922529 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 904283412 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 989794500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988660500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1230123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5813415 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1539,28 +1539,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 71091171c..bbffcb186 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826595 # Number of seconds simulated -sim_ticks 2826594924500 # Number of ticks simulated -final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826654 # Number of seconds simulated +sim_ticks 2826653666000 # Number of ticks simulated +final_tick 2826653666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172097 # Simulator instruction rate (inst/s) -host_op_rate 208779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4050742494 # Simulator tick rate (ticks/s) -host_mem_usage 626976 # Number of bytes of host memory used -host_seconds 697.80 # Real time elapsed on the host -sim_insts 120088860 # Number of instructions simulated -sim_ops 145685275 # Number of ops (including micro ops) simulated +host_inst_rate 170078 # Simulator instruction rate (inst/s) +host_op_rate 206349 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4004321035 # Simulator tick rate (ticks/s) +host_mem_usage 626896 # Number of bytes of host memory used +host_seconds 705.90 # Real time elapsed on the host +sim_insts 120058397 # Number of instructions simulated +sim_ops 145661611 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1324752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1304168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8428096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1325840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1300840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8393920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 175008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 176672 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 427200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 432960 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12249452 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1324752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 175008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1499760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8803008 # Number of bytes written to this memory +system.physmem.bytes_read::total 12220460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1325840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 176672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1502512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8774720 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8820572 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8792284 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131155 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2828 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6765 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 194257 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137547 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193804 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137105 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 468674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 461392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2981713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141496 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 469049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 460205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2969561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 207635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 151136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 62502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 207631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 153171 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4333643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 468674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 530589 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3114351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4323296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 469049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62502 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531552 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3104278 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3120565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3114351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 468674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 467592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2981713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3110492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3104278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 469049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 466405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2969561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 207649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 151136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 207645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 153171 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7454207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 194258 # Number of read requests accepted -system.physmem.writeReqs 141938 # Number of write requests accepted -system.physmem.readBursts 194258 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141938 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12422976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8833536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12249516 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8820572 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7433788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193805 # Number of read requests accepted +system.physmem.writeReqs 141496 # Number of write requests accepted +system.physmem.readBursts 193805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141496 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12392576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue +system.physmem.bytesWritten 8805056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12220524 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8792284 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12130 # Per bank write bursts -system.physmem.perBankRdBursts::1 12140 # Per bank write bursts -system.physmem.perBankRdBursts::2 12480 # Per bank write bursts -system.physmem.perBankRdBursts::3 12151 # Per bank write bursts -system.physmem.perBankRdBursts::4 14882 # Per bank write bursts -system.physmem.perBankRdBursts::5 12677 # Per bank write bursts -system.physmem.perBankRdBursts::6 12709 # Per bank write bursts -system.physmem.perBankRdBursts::7 12606 # Per bank write bursts -system.physmem.perBankRdBursts::8 11844 # Per bank write bursts -system.physmem.perBankRdBursts::9 11522 # Per bank write bursts -system.physmem.perBankRdBursts::10 11334 # Per bank write bursts -system.physmem.perBankRdBursts::11 10175 # Per bank write bursts -system.physmem.perBankRdBursts::12 11497 # Per bank write bursts -system.physmem.perBankRdBursts::13 12486 # Per bank write bursts -system.physmem.perBankRdBursts::14 11961 # Per bank write bursts -system.physmem.perBankRdBursts::15 11515 # Per bank write bursts -system.physmem.perBankWrBursts::0 8842 # Per bank write bursts -system.physmem.perBankWrBursts::1 8923 # Per bank write bursts -system.physmem.perBankWrBursts::2 9151 # Per bank write bursts -system.physmem.perBankWrBursts::3 8834 # Per bank write bursts -system.physmem.perBankWrBursts::4 8743 # Per bank write bursts -system.physmem.perBankWrBursts::5 9257 # Per bank write bursts -system.physmem.perBankWrBursts::6 9174 # Per bank write bursts -system.physmem.perBankWrBursts::7 9022 # Per bank write bursts -system.physmem.perBankWrBursts::8 8380 # Per bank write bursts -system.physmem.perBankWrBursts::9 8199 # Per bank write bursts -system.physmem.perBankWrBursts::10 8228 # Per bank write bursts -system.physmem.perBankWrBursts::11 7543 # Per bank write bursts -system.physmem.perBankWrBursts::12 8493 # Per bank write bursts -system.physmem.perBankWrBursts::13 8795 # Per bank write bursts -system.physmem.perBankWrBursts::14 8486 # Per bank write bursts -system.physmem.perBankWrBursts::15 7954 # Per bank write bursts +system.physmem.perBankRdBursts::0 11925 # Per bank write bursts +system.physmem.perBankRdBursts::1 11855 # Per bank write bursts +system.physmem.perBankRdBursts::2 12297 # Per bank write bursts +system.physmem.perBankRdBursts::3 12187 # Per bank write bursts +system.physmem.perBankRdBursts::4 14909 # Per bank write bursts +system.physmem.perBankRdBursts::5 12660 # Per bank write bursts +system.physmem.perBankRdBursts::6 12587 # Per bank write bursts +system.physmem.perBankRdBursts::7 12794 # Per bank write bursts +system.physmem.perBankRdBursts::8 12033 # Per bank write bursts +system.physmem.perBankRdBursts::9 12070 # Per bank write bursts +system.physmem.perBankRdBursts::10 11247 # Per bank write bursts +system.physmem.perBankRdBursts::11 10141 # Per bank write bursts +system.physmem.perBankRdBursts::12 11323 # Per bank write bursts +system.physmem.perBankRdBursts::13 11835 # Per bank write bursts +system.physmem.perBankRdBursts::14 11954 # Per bank write bursts +system.physmem.perBankRdBursts::15 11817 # Per bank write bursts +system.physmem.perBankWrBursts::0 8684 # Per bank write bursts +system.physmem.perBankWrBursts::1 8734 # Per bank write bursts +system.physmem.perBankWrBursts::2 9001 # Per bank write bursts +system.physmem.perBankWrBursts::3 8790 # Per bank write bursts +system.physmem.perBankWrBursts::4 8747 # Per bank write bursts +system.physmem.perBankWrBursts::5 9254 # Per bank write bursts +system.physmem.perBankWrBursts::6 9144 # Per bank write bursts +system.physmem.perBankWrBursts::7 9206 # Per bank write bursts +system.physmem.perBankWrBursts::8 8582 # Per bank write bursts +system.physmem.perBankWrBursts::9 8592 # Per bank write bursts +system.physmem.perBankWrBursts::10 8144 # Per bank write bursts +system.physmem.perBankWrBursts::11 7450 # Per bank write bursts +system.physmem.perBankWrBursts::12 8375 # Per bank write bursts +system.physmem.perBankWrBursts::13 8211 # Per bank write bursts +system.physmem.perBankWrBursts::14 8456 # Per bank write bursts +system.physmem.perBankWrBursts::15 8209 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 2826594637500 # Total gap between requests +system.physmem.numWrRetry 72 # Number of times write queue was full causing retry +system.physmem.totGap 2826653384500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3091 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190588 # Read request sizes (log2) +system.physmem.readPktSize::6 190135 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137547 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137105 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -189,179 +189,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.267917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.709069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.432600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42654 50.42% 50.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17739 20.97% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6092 7.20% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3470 4.10% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2903 3.43% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1534 1.81% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 962 1.14% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 998 1.18% 90.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8245 9.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84597 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6823 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.448923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.375084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6821 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 164 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.358833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.923887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.724934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42961 50.74% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17699 20.90% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6074 7.17% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3410 4.03% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2753 3.25% 86.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1498 1.77% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.18% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 977 1.15% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8299 9.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84669 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6797 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.488009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.388330 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6795 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6823 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6823 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.229225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.516304 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.191757 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5762 84.45% 84.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 386 5.66% 90.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.13% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 44 0.64% 91.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 244 3.58% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 18 0.26% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.21% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.18% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.25% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.03% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 140 2.05% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.15% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.19% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6823 # Writes before turning the bus around for reads -system.physmem.totQLat 10063104165 # Total ticks spent queuing -system.physmem.totMemAccLat 13702647915 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 970545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51842.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6797 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.241136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.514528 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.610339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 6111 89.91% 89.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 128 1.88% 91.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 273 4.02% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 31 0.46% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 13 0.19% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.21% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 146 2.15% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 13 0.19% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 11 0.16% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 7 0.10% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.12% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 5 0.07% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.12% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.09% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-327 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6797 # Writes before turning the bus around for reads +system.physmem.totQLat 9919718835 # Total ticks spent queuing +system.physmem.totMemAccLat 13550356335 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 968170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51228.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70592.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 69978.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing -system.physmem.readRowHits 161915 # Number of row buffer hits during reads -system.physmem.writeRowHits 85621 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.03 # Row buffer hit rate for writes -system.physmem.avgGap 8407579.62 # Average gap between requests -system.physmem.pageHitRate 74.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 318172680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169112790 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 726673500 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 375558120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4535428560.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4774700760 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 244257600 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9148762200 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6477825120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667571113185 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 694343780025 # Total energy per rank (pJ) -system.physmem_0.averagePower 245.646723 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2815396783365 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 428149701 # Time in different power states -system.physmem_0.memoryStateTime::REF 1926538000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2778550744250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16869300047 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8757031934 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 20063160568 # Time in different power states -system.physmem_1.actEnergy 285849900 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 151932825 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 659264760 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 344927160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4569848400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4671042840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 250741920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8727797820 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6816319680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667684488600 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 694164121065 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.583162 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2815694283339 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 440101951 # Time in different power states -system.physmem_1.memoryStateTime::REF 1941710000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778803468000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17750764755 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8518829210 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 19140050584 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 161407 # Number of row buffer hits during reads +system.physmem.writeRowHits 85137 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.87 # Row buffer hit rate for writes +system.physmem.avgGap 8430196.70 # Average gap between requests +system.physmem.pageHitRate 74.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 316180620 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 168053985 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 722667960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373543200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4556326320.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4729873110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240133440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9128983770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6579538080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667569876735 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 694387365510 # Total energy per rank (pJ) +system.physmem_0.averagePower 245.657037 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2815586462334 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 417040689 # Time in different power states +system.physmem_0.memoryStateTime::REF 1935564000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2778497008500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 17134268560 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8650044977 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 20019739274 # Time in different power states +system.physmem_1.actEnergy 288356040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 153264870 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 659878800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 344619180 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4568619120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4738351860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 236664480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8828064240 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6766632480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667633644195 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 694220207745 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.597901 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2815641624954 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 407791169 # Time in different power states +system.physmem_1.memoryStateTime::REF 1940956000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778660280000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17621547350 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8663293877 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19359797604 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -380,30 +366,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53161527 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24432585 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 935077 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32150468 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13984916 # Number of BTB hits +system.cpu0.branchPred.lookups 53099847 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24413538 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 933900 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32114969 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13973138 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.498328 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15489494 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33173 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10133739 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9977658 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 156081 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 49006 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 43.509735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15469071 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33231 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10119740 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9963994 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155746 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 49057 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -433,83 +419,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 66483 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 66483 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25519 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19054 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 21910 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44573 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 499.046508 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3114.296115 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43354 97.27% 97.27% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 917 2.06% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 116 0.26% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 24 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65583 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65583 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25222 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18949 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 21412 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44171 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 487.310679 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3087.040611 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 42986 97.32% 97.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 897 2.03% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 93 0.21% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 33 0.07% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 15 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44573 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16394 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9809.718618 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14883 90.78% 90.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1339 8.17% 98.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 129 0.79% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 18 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.01% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 6 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::245760-262143 16 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16394 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 86404933652 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.566419 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.506005 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 86345641152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 41095500 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 8202000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4970000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2695000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 946000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 940000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 429500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 86404933652 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5203 78.33% 78.33% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1439 21.67% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6642 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66483 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44171 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16005 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11349.047173 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9735.111358 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7638.174811 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14581 91.10% 91.10% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1176 7.35% 98.45% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 210 1.31% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 7 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.07% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16005 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 82168586356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.591771 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.502145 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 82111702356 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 39388000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7963500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4902500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2427000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 777000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 938000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 463500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 82168586356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5127 78.72% 78.72% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1386 21.28% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6513 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65583 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66483 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6642 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6513 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6642 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73125 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72096 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23680324 # DTB read hits -system.cpu0.dtb.read_misses 56461 # DTB read misses -system.cpu0.dtb.write_hits 17598903 # DTB write hits -system.cpu0.dtb.write_misses 10022 # DTB write misses +system.cpu0.dtb.read_hits 23662283 # DTB read hits +system.cpu0.dtb.read_misses 55655 # DTB read misses +system.cpu0.dtb.write_hits 17589226 # DTB write hits +system.cpu0.dtb.write_misses 9928 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2246 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3427 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2234 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 902 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23736785 # DTB read accesses -system.cpu0.dtb.write_accesses 17608925 # DTB write accesses +system.cpu0.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23717938 # DTB read accesses +system.cpu0.dtb.write_accesses 17599154 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41279227 # DTB hits -system.cpu0.dtb.misses 66483 # DTB misses -system.cpu0.dtb.accesses 41345710 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 41251509 # DTB hits +system.cpu0.dtb.misses 65583 # DTB misses +system.cpu0.dtb.accesses 41317092 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -539,58 +526,61 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 11041 # Table walker walks requested -system.cpu0.itb.walker.walksShort 11041 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4028 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5930 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1083 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9958 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 410.574413 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2129.037976 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9588 96.28% 96.28% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 186 1.87% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 118 1.18% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.38% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 5 0.05% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 10907 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10907 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3899 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5942 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1066 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9841 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 431.460217 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2241.549622 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9464 96.17% 96.17% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 172 1.75% 97.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 49 0.50% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 6 0.06% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.19% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9958 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3663 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5522.553888 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 663 18.10% 18.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2695 73.57% 91.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 173 4.72% 96.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 79 2.16% 98.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::total 9841 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12380.384088 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11386.423562 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5549.123195 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 601 16.49% 16.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2727 74.81% 91.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 175 4.80% 96.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 87 2.39% 98.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3663 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21980185712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.834654 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.371618 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3635314000 16.54% 16.54% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18343952712 83.46% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 868500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 50500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21980185712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2243 86.94% 86.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 337 13.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2580 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 22038229712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.837207 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.369334 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3588883500 16.28% 16.28% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18448211212 83.71% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 1065000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22038229712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2246 87.09% 87.09% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 333 12.91% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11041 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10907 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10907 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2580 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2580 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13621 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72829698 # ITB inst hits -system.cpu0.itb.inst_misses 11041 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13486 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72758108 # ITB inst hits +system.cpu0.itb.inst_misses 10907 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -599,160 +589,160 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2282 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1929 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1937 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72840739 # ITB inst accesses -system.cpu0.itb.hits 72829698 # DTB hits -system.cpu0.itb.misses 11041 # DTB misses -system.cpu0.itb.accesses 72840739 # DTB accesses -system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1456796210.372727 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23672658216.113400 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1093 58.45% 58.45% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.28% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 72769015 # ITB inst accesses +system.cpu0.itb.hits 72758108 # DTB hits +system.cpu0.itb.misses 10907 # DTB misses +system.cpu0.itb.accesses 72769015 # DTB accesses +system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1484523232.318801 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23903491534.812244 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1057 57.60% 57.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.13% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499970757520 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 102386011103 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 204773026 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 102553534695 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724100131305 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 205108250 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20714269 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 196101622 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53161527 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39452068 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 175603283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5698298 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148281 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 420719 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 418648 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 100050 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72829386 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 258768 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5384 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 200312046 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.196487 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.307164 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20843459 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 195936196 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53099847 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39406203 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 175823444 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5691288 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148299 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 58157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 416860 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 413792 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 98564 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72757810 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257476 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5315 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 200648219 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.193498 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.306871 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 95293979 47.57% 47.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30393228 15.17% 62.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14596992 7.29% 70.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 60027847 29.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 95712766 47.70% 47.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30373277 15.14% 62.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14586568 7.27% 70.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 59975608 29.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 200312046 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.259612 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.957654 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25714917 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108196913 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58914772 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4966892 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2518552 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3065050 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 334861 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154468947 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3822056 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2518552 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34338225 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12857218 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83619486 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55122113 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11856452 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137773765 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1037168 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1494015 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 163408 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 59807 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7647937 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141868428 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 635547314 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152852010 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9442 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130675877 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11192540 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2699923 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2556575 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22590232 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24607184 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19088589 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1696558 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2229617 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134839557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1714900 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132985122 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 452743 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10598058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21682682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 119247 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 200312046 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.663890 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.961819 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 200648219 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.258887 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.955282 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25818393 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108480918 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58863420 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4969304 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2516184 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3061987 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 333558 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154376244 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3806825 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2516184 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34429607 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12873889 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83899455 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55085453 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11843631 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137696782 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1037438 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1493634 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 164344 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 57817 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7635337 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141807029 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 635200062 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152788581 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130609661 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11197357 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2697375 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2554361 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22576827 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24592847 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19077592 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1691886 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2320615 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134759616 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1714081 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132897861 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 450666 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10595447 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21697472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 119702 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 200648219 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.662343 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.961216 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 123495652 61.65% 61.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33655276 16.80% 78.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31282184 15.62% 94.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10750314 5.37% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1128564 0.56% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 56 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 123885975 61.74% 61.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33618455 16.75% 78.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31280513 15.59% 94.09% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10734778 5.35% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1128444 0.56% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 200312046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 200648219 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10816144 43.95% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 73 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5625612 22.86% 66.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8160344 33.16% 99.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 2838 0.01% 99.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 7018 0.03% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10806493 43.96% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 67 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5620315 22.86% 66.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8146085 33.14% 99.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 2848 0.01% 99.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 7137 0.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89847428 67.56% 67.56% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 110447 0.08% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89788621 67.56% 67.56% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 110178 0.08% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued @@ -767,7 +757,7 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued @@ -777,102 +767,102 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8088 0.01% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24366318 18.32% 85.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18639513 14.02% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 3092 0.00% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 8185 0.01% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24348007 18.32% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18629393 14.02% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 8193 0.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued -system.cpu0.iq.rate 0.649427 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24612029 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185074 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 491314637 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32424 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 132897861 # Type of FU issued +system.cpu0.iq.rate 0.647940 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24582945 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.184976 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 491444928 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 147076893 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129373990 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32623 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11320 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157573738 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21140 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 157457242 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21291 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 367347 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2461 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19267 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 901714 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1915298 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2464 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19139 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 903377 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 120909 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362204 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121005 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 360360 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2518552 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1651189 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 246744 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136707359 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2516184 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1671558 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 251575 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136626375 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24607184 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19088589 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876464 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261441 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 661747 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131953487 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 965274 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24592847 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19077592 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 875905 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27780 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 199746 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19139 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 262595 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398520 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 661115 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131868425 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23910267 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 963966 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152902 # number of nop insts executed -system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25613561 # Number of branches executed -system.cpu0.iew.exec_stores 18487461 # Number of stores executed -system.cpu0.iew.exec_rate 0.644389 # Inst execution rate -system.cpu0.iew.wb_sent 131398392 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 66052971 # num instructions producing a value -system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.632234 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618630 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9569777 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1595653 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 604480 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 197147849 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.639512 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.336739 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152678 # number of nop insts executed +system.cpu0.iew.exec_refs 42387378 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25593933 # Number of branches executed +system.cpu0.iew.exec_stores 18477111 # Number of stores executed +system.cpu0.iew.exec_rate 0.642921 # Inst execution rate +system.cpu0.iew.wb_sent 131315181 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129383707 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 66018205 # num instructions producing a value +system.cpu0.iew.wb_consumers 106739719 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.630807 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618497 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9567606 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1594379 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 604440 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 197485844 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.638022 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.337140 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 136598241 69.29% 69.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33559109 17.02% 86.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12649949 6.42% 92.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3238672 1.64% 94.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4912875 2.49% 96.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2898818 1.47% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1203082 0.61% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 557487 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1529616 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 137054336 69.40% 69.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33455560 16.94% 86.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12646051 6.40% 92.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3243439 1.64% 94.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4914257 2.49% 96.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2777569 1.41% 98.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1312207 0.66% 98.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 555201 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1527224 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 197147849 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 104125280 # Number of instructions committed -system.cpu0.commit.committedOps 126078442 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 197485844 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 104056922 # Number of instructions committed +system.cpu0.commit.committedOps 126000293 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40877611 # Number of memory references committed -system.cpu0.commit.loads 22690736 # Number of loads committed -system.cpu0.commit.membars 648887 # Number of memory barriers committed -system.cpu0.commit.branches 25008531 # Number of branches committed +system.cpu0.commit.refs 40851763 # Number of memory references committed +system.cpu0.commit.loads 22677548 # Number of loads committed +system.cpu0.commit.membars 647714 # Number of memory barriers committed +system.cpu0.commit.branches 24989662 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 110051272 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4840996 # Number of function calls committed. +system.cpu0.commit.int_insts 109983283 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4835482 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 85084925 67.49% 67.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 108043 0.09% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 85032586 67.49% 67.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 107857 0.09% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction @@ -898,752 +888,759 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8087 0.01% 67.58% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22688480 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18179427 14.42% 99.99% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22675292 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18166767 14.42% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1529616 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 307952651 # The number of ROB reads -system.cpu0.rob.rob_writes 274451297 # The number of ROB writes -system.cpu0.timesIdled 137106 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4460980 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5448417066 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 104003228 # Number of Instructions Simulated -system.cpu0.committedOps 125956390 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.968910 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.968910 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.507895 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads -system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8197 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 465685860 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes -system.cpu0.misc_regfile_reads 394201898 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 711042 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.782039 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37710898 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 711554 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.997943 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 126000293 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1527224 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 308240127 # The number of ROB reads +system.cpu0.rob.rob_writes 274288918 # The number of ROB writes +system.cpu0.timesIdled 136024 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4460031 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5448199500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 103934870 # Number of Instructions Simulated +system.cpu0.committedOps 125878241 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.973431 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.973431 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.506732 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.506732 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142861191 # number of integer regfile reads +system.cpu0.int_regfile_writes 81742978 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8188 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2265 # number of floating regfile writes +system.cpu0.cc_regfile_reads 465378109 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49818068 # number of cc regfile writes +system.cpu0.misc_regfile_reads 395692849 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1225433 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 712812 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.246418 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37680999 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713324 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.824522 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.782039 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972231 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.972231 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.246418 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975091 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.975091 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81278285 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81278285 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21483760 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21483760 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15003255 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15003255 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307803 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307803 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363087 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363087 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361616 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36487015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36487015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36794818 # number of overall hits -system.cpu0.dcache.overall_hits::total 36794818 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 647587 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 647587 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1894796 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1894796 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148778 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 148778 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25560 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25560 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20165 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20165 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2542383 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2542383 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2691161 # number of overall misses -system.cpu0.dcache.overall_misses::total 2691161 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9361035000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9361035000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33017805879 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 33017805879 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412521000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 412521000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 476921000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 476921000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 443000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 443000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 42378840879 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42378840879 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 42378840879 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42378840879 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22131347 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22131347 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16898051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456581 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456581 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388647 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388647 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381781 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381781 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39029398 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39029398 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39485979 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39485979 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029261 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029261 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112131 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.112131 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065767 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065767 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052818 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052818 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065140 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065140 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068155 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068155 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81225267 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81225267 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21467047 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21467047 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14989931 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14989931 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307917 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307917 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363108 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363108 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361279 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361279 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36456978 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36456978 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36764895 # number of overall hits +system.cpu0.dcache.overall_hits::total 36764895 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 649306 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 649306 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1896144 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1896144 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148546 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 148546 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25295 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25295 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20257 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20257 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2545450 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2545450 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2693996 # number of overall misses +system.cpu0.dcache.overall_misses::total 2693996 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9384044500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9384044500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32956196365 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32956196365 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411578000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 411578000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 478843500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 478843500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 432000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 432000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 42340240865 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42340240865 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 42340240865 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42340240865 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22116353 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22116353 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16886075 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16886075 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456463 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456463 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388403 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388403 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381536 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381536 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39002428 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39002428 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39458891 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39458891 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029359 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029359 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112290 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.112290 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325428 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325428 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065126 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065126 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053093 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053093 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065264 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065264 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068273 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.068273 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14452.422279 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14452.422279 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17380.640060 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17380.640060 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16271.120775 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.120775 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23638.421286 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23638.421286 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4996394 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 202489 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24.674891 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 711042 # number of writebacks -system.cpu0.dcache.writebacks::total 711042 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260652 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260652 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569869 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1569869 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18798 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18798 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830521 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1830521 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830521 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1830521 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386935 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386935 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324927 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324927 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102518 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102518 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20165 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20165 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711862 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711862 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 814380 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 814380 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60239 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5003581000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5003581000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626488404 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626488404 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1706140000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1706140000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107183000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107183000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 456767000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 456767000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 432000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 432000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11630069404 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11630069404 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13336209404 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13336209404 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624172500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624172500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6624172500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6624172500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017484 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017484 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224534 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224534 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052818 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052818 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018239 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020625 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020625 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12931.321798 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12931.321798 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16633.695757 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16633.695757 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15716.519574 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15716.519574 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 757 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4969613 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201973 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.023810 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24.605333 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 712815 # number of writebacks +system.cpu0.dcache.writebacks::total 712815 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260774 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260774 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570443 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1570443 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18576 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18576 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1831217 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1831217 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1831217 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1831217 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388532 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 388532 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325701 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325701 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102377 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102377 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6719 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6719 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20257 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20257 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 714233 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 714233 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 816610 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 816610 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32008 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60690 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5031436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5031436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6631878895 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6631878895 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1714108500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1714108500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107735000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107735000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458598500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458598500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 420000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 420000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663315395 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11663315395 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13377423895 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13377423895 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6681974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6681974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6681974000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6681974000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019288 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019288 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224283 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224283 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017299 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017299 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053093 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053093 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018313 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018313 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020695 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020695 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12949.863846 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12949.863846 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20361.862245 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20361.862245 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16743.101478 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16743.101478 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16034.380116 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16034.380116 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22639.013674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22639.013674 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1252192 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.757674 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71518552 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1252703 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 57.091387 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6585004000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757674 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16329.846696 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16329.846696 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.655741 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.655741 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208759.497626 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208759.497626 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110100.082386 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110100.082386 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1249331 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757700 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71450204 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1249842 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.167389 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6584638000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757700 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 125 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146904258 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146904258 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71518555 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71518555 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71518555 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71518555 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71518555 # number of overall hits -system.cpu0.icache.overall_hits::total 71518555 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1307201 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1307201 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1307201 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1307201 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1307201 # number of overall misses -system.cpu0.icache.overall_misses::total 1307201 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14223203310 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14223203310 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14223203310 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14223203310 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14223203310 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14223203310 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72825756 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72825756 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72825756 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72825756 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72825756 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72825756 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10880.655163 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10880.655163 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10880.655163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10880.655163 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1774060 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1996 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 116060 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 146758301 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146758301 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 71450207 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71450207 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71450207 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71450207 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71450207 # number of overall hits +system.cpu0.icache.overall_hits::total 71450207 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1303999 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1303999 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1303999 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1303999 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1303999 # number of overall misses +system.cpu0.icache.overall_misses::total 1303999 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14174791933 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14174791933 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14174791933 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14174791933 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14174791933 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14174791933 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 72754206 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 72754206 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 72754206 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 72754206 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 72754206 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 72754206 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017923 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017923 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017923 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017923 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017923 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017923 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10870.247549 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10870.247549 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10870.247549 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10870.247549 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1760744 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1640 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 114723 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.285714 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 153.538462 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1252192 # number of writebacks -system.cpu0.icache.writebacks::total 1252192 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54454 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54454 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54454 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54454 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54454 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54454 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1252747 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1252747 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1252747 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1252747 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1252747 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1252747 # number of overall MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.347786 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 126.153846 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1249331 # number of writebacks +system.cpu0.icache.writebacks::total 1249331 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54109 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54109 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54109 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54109 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54109 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54109 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1249890 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1249890 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1249890 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1249890 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1249890 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1249890 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12840860811 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12840860811 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12840860811 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12840860811 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12840860811 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12840860811 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12814231927 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12814231927 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12814231927 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12814231927 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12814231927 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12814231927 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017202 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017202 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017202 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10250.162891 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017180 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017180 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017180 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10252.287743 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846192 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1848788 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2354 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846767 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1849379 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2365 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238916 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 272116 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15645.226913 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1883031 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 287760 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.543755 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236461 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 270933 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15649.129225 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1883932 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 286558 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.574348 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14543.018555 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.670469 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.025524 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1089.512365 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.887635 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000712 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066499 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954909 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15373 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14546.798617 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.022626 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137647 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1090.170335 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.887866 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000734 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066539 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.955147 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 298 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15316 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 145 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 80 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 318 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1446 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7384 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4965 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1260 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 67637085 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 67637085 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55351 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13068 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 68419 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481133 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481133 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1450737 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1450737 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220760 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 220760 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1181751 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1181751 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388592 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 388592 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55351 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13068 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1181751 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609352 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1859522 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55351 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13068 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1181751 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609352 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1859522 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 707 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55745 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55745 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20165 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20165 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48603 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48603 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70953 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 70953 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107504 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 107504 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 70953 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 156107 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 227767 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 70953 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 156107 # number of overall misses -system.cpu0.l2cache.overall_misses::total 227767 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15335000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4771500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 20106500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 35671000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 35671000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9320000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9320000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 415000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 415000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3386740000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 3386740000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3777812500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3777812500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3493890998 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3493890998 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15335000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4771500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3777812500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6880630998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 10678549998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15335000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4771500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3777812500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6880630998 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 10678549998 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55858 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13268 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 69126 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481133 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481133 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450737 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1450737 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20165 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20165 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269363 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269363 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1252704 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1252704 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 496096 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 496096 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55858 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13268 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1252704 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 765459 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2087289 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55858 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13268 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1252704 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 765459 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2087289 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015074 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.010228 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1433 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7528 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4690 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018188 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934814 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 67601036 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 67601036 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54858 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13069 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 67927 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 483646 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 483646 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1447155 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1447155 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221212 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 221212 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1179291 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1179291 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 390010 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 390010 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54858 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13069 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1179291 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 611222 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1858440 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54858 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13069 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1179291 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 611222 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1858440 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 514 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 209 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 723 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55801 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55801 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20257 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20257 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48873 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 48873 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70560 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 70560 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107498 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 107498 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 514 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 209 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 70560 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 156371 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 227654 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 514 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 209 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 70560 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 156371 # number of overall misses +system.cpu0.l2cache.overall_misses::total 227654 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15837500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5057000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 20894500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37580500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 37580500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9656000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9656000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 401500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 401500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3379601499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 3379601499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3771387500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3771387500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3519117997 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3519117997 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15837500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5057000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3771387500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6898719496 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 10691001496 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15837500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5057000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3771387500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6898719496 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 10691001496 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55372 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13278 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 68650 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483646 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 483646 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1447155 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1447155 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55802 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55802 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20257 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20257 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270085 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 270085 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1249851 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1249851 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497508 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 497508 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55372 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13278 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1249851 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 767593 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2086094 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55372 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13278 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1249851 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 767593 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2086094 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015740 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.010532 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180437 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180437 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056640 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056640 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216700 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216700 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015074 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056640 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203939 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.109121 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015074 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056640 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203939 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.109121 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.500000 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28439.179632 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 639.895955 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 639.895955 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 462.186958 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 462.186958 # average SCUpgradeReq miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180954 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180954 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056455 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056455 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216073 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216073 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015740 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056455 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203716 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.109129 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015740 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056455 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203716 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.109129 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24196.172249 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28899.723375 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 673.473594 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 673.473594 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 476.674730 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 476.674730 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69681.706891 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69681.706891 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53243.872704 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53243.872704 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32500.102303 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32500.102303 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 46883.657413 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 46883.657413 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69150.686453 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69150.686453 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53449.369331 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53449.369331 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32736.590420 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32736.590420 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 46961.623762 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 46961.623762 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 28.714286 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10599 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 230738 # number of writebacks -system.cpu0.l2cache.writebacks::total 230738 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5942 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5942 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 36 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 36 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 741 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 741 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 36 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6683 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6721 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 36 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6683 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6721 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 198 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 705 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262695 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 262695 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55745 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55745 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20165 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20165 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70917 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70917 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106763 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106763 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 198 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70917 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149424 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 221046 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 198 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70917 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149424 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262695 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 483741 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10601 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 229825 # number of writebacks +system.cpu0.l2cache.writebacks::total 229825 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5836 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 5836 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 788 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 788 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6624 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6668 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6624 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6668 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 513 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 206 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 262614 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55801 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55801 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20257 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20257 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43037 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43037 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70520 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70520 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106710 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106710 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 513 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 206 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70520 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149747 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 220986 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 513 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 206 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70520 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149747 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 483600 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34790 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35016 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63247 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3546000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 15839000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17363724717 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 962038500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 962038500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304268499 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304268499 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 349000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 349000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2236694000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2236694000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3350952500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3350952500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2808325998 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2808325998 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3546000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3350952500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5045019998 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8411811498 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3546000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3350952500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5045019998 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 25775536215 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63698 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3770500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 16512000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17165691219 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 965407999 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 965407999 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305528000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305528000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 329500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 329500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2246676499 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2246676499 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3346200500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3346200500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2833954497 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2833954497 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3770500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3346200500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5080630996 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8443343496 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3770500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3346200500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5080630996 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25609034715 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369584000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6634670000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6425579500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6690665500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6369584000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6634670000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010199 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6425579500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6690665500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010473 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158377 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158377 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056611 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215206 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.215206 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105901 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159346 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159346 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056423 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214489 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214489 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105933 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231756 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231821 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22965.229485 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65364.722441 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17300.908568 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300.908568 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15082.588735 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.588735 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52203.371494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52203.371494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47450.375780 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26557.534411 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26557.534411 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38207.594581 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52954.993207 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200749.172082 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191074.523075 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4079155 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2060991 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31388 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 213571 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 211819 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1752 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 114320 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1911393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28457 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28457 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 712151 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1482098 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 89271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 330960 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42590 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113358 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1252747 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 585259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3763658 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2614734 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29156 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119485 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6527033 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160361408 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98721444 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53072 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223432 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259359356 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 926756 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18862496 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3052726 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.087981 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.285286 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105875.424287 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105037.293165 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4075722 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058160 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32446 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 214641 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212781 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1860 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 113949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1910077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28682 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28682 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 713807 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1478497 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 89121 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 330731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288564 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1249890 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3237 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3755087 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2622795 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 118492 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6525435 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159995712 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99013924 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53112 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 221488 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259284236 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 927446 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18848064 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3052004 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.088140 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.285640 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2785896 91.26% 91.26% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 265078 8.68% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1752 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2784861 91.25% 91.25% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 265283 8.69% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1860 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3052726 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4077518993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3052004 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4075635489 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113316466 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114371967 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1882577097 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1878285609 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1233739845 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1237556949 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15895485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15793479 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63655441 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63149938 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4630228 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2728889 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 266806 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2406642 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1541904 # Number of BTB hits +system.cpu1.branchPred.lookups 4617850 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2715513 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 269466 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2413279 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1525969 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.068690 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 874664 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7405 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 249240 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 213278 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 35962 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10619 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 63.232183 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 876806 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7196 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 247807 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 212871 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 34936 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10588 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1673,93 +1670,95 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21137 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21137 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8393 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5852 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6892 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14245 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 645.419445 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3393.467484 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13571 95.27% 95.27% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 196 1.38% 96.64% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 230 1.61% 98.26% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 102 0.72% 98.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.20% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 27 0.19% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 10 0.07% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.45% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 10 0.07% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14245 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5483 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9975.216104 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6340.433585 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1893 34.52% 34.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2927 53.38% 87.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 431 7.86% 95.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 169 3.08% 98.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 33 0.60% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.44% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5483 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 77531116060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.220578 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.418371 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 60476667848 78.00% 78.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 17032378712 21.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12865500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 4248000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1183000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 1086000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 1322500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 461500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 217000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 174500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 136000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 33500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 198000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 27000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 77531116060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1915 74.80% 74.80% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 645 25.20% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2560 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21137 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21585 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21585 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8697 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5905 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6983 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14602 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 620.599918 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3321.361869 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13932 95.41% 95.41% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.56% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 109 0.75% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 26 0.18% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 7 0.05% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 6 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14602 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5436 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11628.403238 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9929.194928 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8303.343609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1858 34.18% 34.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2915 53.62% 87.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 446 8.20% 96.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 133 2.45% 98.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 34 0.63% 99.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.46% 99.54% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.11% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 11 0.20% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 7 0.13% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5436 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 81885681356 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.177146 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.385706 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 67426452132 82.34% 82.34% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 14437765724 17.63% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12512000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 4018500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1336000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 984500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1256500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 435000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 231000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 183500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 98500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 31000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 125000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 29500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 188500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 81885681356 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1913 75.20% 75.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 631 24.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21585 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21137 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2560 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21585 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2560 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 23697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24129 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4149269 # DTB read hits -system.cpu1.dtb.read_misses 18244 # DTB read misses -system.cpu1.dtb.write_hits 3464998 # DTB write hits -system.cpu1.dtb.write_misses 2893 # DTB write misses +system.cpu1.dtb.read_hits 4154069 # DTB read hits +system.cpu1.dtb.read_misses 18709 # DTB read misses +system.cpu1.dtb.write_hits 3480708 # DTB write hits +system.cpu1.dtb.write_misses 2876 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1955 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1944 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 52 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 410 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4167513 # DTB read accesses -system.cpu1.dtb.write_accesses 3467891 # DTB write accesses +system.cpu1.dtb.perms_faults 381 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4172778 # DTB read accesses +system.cpu1.dtb.write_accesses 3483584 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7614267 # DTB hits -system.cpu1.dtb.misses 21137 # DTB misses -system.cpu1.dtb.accesses 7635404 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7634777 # DTB hits +system.cpu1.dtb.misses 21585 # DTB misses +system.cpu1.dtb.accesses 7656362 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1789,63 +1788,64 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5745 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5745 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2522 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2644 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 579 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5166 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 354.045683 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2100.129090 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 4967 96.15% 96.15% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.83% 96.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 47 0.91% 97.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.41% 98.30% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 19 0.37% 98.66% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 23 0.45% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 19 0.37% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 7 0.14% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.12% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 1 0.02% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 4 0.08% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 3 0.06% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5166 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1734 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5990.262254 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 321 18.51% 18.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1223 70.53% 89.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 108 6.23% 95.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 58 3.34% 98.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 14 0.81% 99.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 5 0.29% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 5903 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5903 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2681 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2633 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 589 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5314 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 359.427926 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2179.481540 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 5115 96.26% 96.26% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 44 0.83% 97.08% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 38 0.72% 97.80% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.40% 98.19% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 22 0.41% 98.61% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 26 0.49% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 16 0.30% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.09% 99.49% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 7 0.13% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.06% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 3 0.06% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.08% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5314 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1751 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12219.588806 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11149.776616 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5813.276337 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 298 17.02% 17.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 71.96% 88.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 107 6.11% 95.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.88% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.46% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.29% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.06% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1734 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 17381208916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.871345 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.334946 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2236929264 12.87% 12.87% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 15143532152 87.13% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 747500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 17381208916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 985 85.28% 85.28% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.72% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1751 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 17441612916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.860137 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.346964 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2440154764 13.99% 13.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 15000736652 86.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 721500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 17441612916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 992 85.37% 85.37% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.63% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1162 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5745 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5745 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5903 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5903 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6900 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8164971 # ITB inst hits -system.cpu1.itb.inst_misses 5745 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1162 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1162 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7065 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8146400 # ITB inst hits +system.cpu1.itb.inst_misses 5903 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1854,1041 +1854,1053 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1122 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1127 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8170716 # ITB inst accesses -system.cpu1.itb.hits 8164971 # DTB hits -system.cpu1.itb.misses 5745 # DTB misses -system.cpu1.itb.accesses 8170716 # DTB accesses -system.cpu1.numPwrStateTransitions 5463 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2732 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1028238405.084919 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25963867647.326580 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1944 71.16% 71.16% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 782 28.62% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 8152303 # ITB inst accesses +system.cpu1.itb.hits 8146400 # DTB hits +system.cpu1.itb.misses 5903 # DTB misses +system.cpu1.itb.accesses 8152303 # DTB accesses +system.cpu1.numPwrStateTransitions 5563 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2782 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1009807188.625809 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25701428342.991928 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1977 71.06% 71.06% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.72% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959984033604 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2732 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17447601808 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34895980 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 959983958132 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2782 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17370067243 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809283598757 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 34740953 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8706814 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24545743 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4630228 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2629846 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 24236084 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 776070 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 77763 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 35252 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 165739 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 299959 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23654 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8163829 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 107624 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2029 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 33933300 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.881300 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.218696 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8935699 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24503906 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4617850 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2615646 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 23842655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 779742 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 80208 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 31335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 166914 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 295220 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22708 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8145254 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 111581 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 33764610 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.884848 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.220160 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20192419 59.51% 59.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4836103 14.25% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1645003 4.85% 78.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7259775 21.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20042304 59.36% 59.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4827845 14.30% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1634677 4.84% 78.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7259784 21.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 33933300 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.132687 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.703397 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7185713 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16755217 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8648276 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1081250 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 262844 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 705359 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 127834 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23145137 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1030723 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 262844 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8592488 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2388926 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11714810 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8302740 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2671492 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 21985761 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 184128 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 260119 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36299 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16259 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1667149 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 21955593 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 102445019 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25352022 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19598713 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2356880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 406325 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 333389 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2861472 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4400097 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3772059 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 619281 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 624174 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21175375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 559463 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 20999121 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 90560 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2005952 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4627057 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 43664 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 33933300 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.618835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.947092 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 33764610 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.132922 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.705332 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7349000 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16390631 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8692861 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1069281 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 262837 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 706015 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129761 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23185557 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1033744 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 262837 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8748161 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2379135 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11360118 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8342372 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2671987 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 22035257 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 184232 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 261771 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36717 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15492 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1677749 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 21981180 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 102687971 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25443797 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 19631101 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2350079 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 398085 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 327427 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2832658 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4406260 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3798525 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 616794 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 601017 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21230855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 553061 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21048993 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91520 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2000545 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4635811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 42283 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 33764610 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.623404 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.949604 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21549433 63.51% 63.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6114741 18.02% 81.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4178352 12.31% 93.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1835426 5.41% 99.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 255342 0.75% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21364495 63.27% 63.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6105280 18.08% 81.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4197946 12.43% 93.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1839743 5.45% 99.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 257138 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 33933300 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 33764610 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1405486 29.50% 29.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 669 0.01% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1601939 33.63% 63.15% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1753523 36.81% 99.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 663 0.01% 99.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 1366 0.03% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1397917 29.28% 29.28% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 677 0.01% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1598296 33.48% 62.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1774858 37.18% 99.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 659 0.01% 99.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 1349 0.03% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 12960054 61.72% 61.72% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 27621 0.13% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4355305 20.74% 82.60% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3650681 17.38% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 724 0.00% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 1405 0.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 12978869 61.66% 61.66% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 28429 0.14% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4359753 20.71% 82.52% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3676453 17.47% 99.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 99.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 1404 0.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued -system.cpu1.iq.rate 0.601763 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4763646 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226850 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 80779454 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6294 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 25758543 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4158 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 21048993 # Type of FU issued +system.cpu1.iq.rate 0.605884 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4773756 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226793 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 80721609 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 23791762 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20591914 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6263 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2082 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 25818553 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4130 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87577 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 640 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9457 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 249525 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 404936 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 702 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9416 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 250549 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40585 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 76754 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40531 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 75671 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 262844 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 543765 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 103558 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 21775845 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 262837 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 524383 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 105080 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 21825012 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4400097 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3772059 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 296163 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7694 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 88949 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9457 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 34239 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118390 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 152629 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 20771745 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4261184 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 206260 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4406260 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3798525 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 290384 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7837 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 90528 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9416 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33554 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 119405 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 152959 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 20820702 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4265911 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 206727 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41007 # number of nop insts executed -system.cpu1.iew.exec_refs 7864490 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3010595 # Number of branches executed -system.cpu1.iew.exec_stores 3603306 # Number of stores executed -system.cpu1.iew.exec_rate 0.595248 # Inst execution rate -system.cpu1.iew.wb_sent 20641556 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20543049 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10275425 # num instructions producing a value -system.cpu1.iew.wb_consumers 16109782 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.588694 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637838 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1795274 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 515799 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 141615 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33527734 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.589415 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.349112 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41096 # number of nop insts executed +system.cpu1.iew.exec_refs 7893380 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3012609 # Number of branches executed +system.cpu1.iew.exec_stores 3627469 # Number of stores executed +system.cpu1.iew.exec_rate 0.599313 # Inst execution rate +system.cpu1.iew.wb_sent 20691409 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20593701 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10296891 # num instructions producing a value +system.cpu1.iew.wb_consumers 16154886 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.592779 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637386 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1790740 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 510778 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 142432 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33360276 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.594007 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.352197 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24087304 71.84% 71.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5545630 16.54% 88.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1675188 5.00% 93.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 660381 1.97% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 508267 1.52% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 330740 0.99% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 223183 0.67% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 117603 0.35% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 379438 1.13% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23884731 71.60% 71.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5569703 16.70% 88.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1678289 5.03% 93.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 665043 1.99% 95.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 510124 1.53% 96.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 336609 1.01% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 218533 0.66% 98.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 117875 0.35% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 379369 1.14% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33527734 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16118487 # Number of instructions committed -system.cpu1.commit.committedOps 19761740 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33360276 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16156383 # Number of instructions committed +system.cpu1.commit.committedOps 19816226 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7516733 # Number of memory references committed -system.cpu1.commit.loads 3994199 # Number of loads committed -system.cpu1.commit.membars 208310 # Number of memory barriers committed -system.cpu1.commit.branches 2858693 # Number of branches committed +system.cpu1.commit.refs 7549300 # Number of memory references committed +system.cpu1.commit.loads 4001324 # Number of loads committed +system.cpu1.commit.membars 208499 # Number of memory barriers committed +system.cpu1.commit.branches 2862007 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17575462 # Number of committed integer instructions. -system.cpu1.commit.function_calls 459876 # Number of function calls committed. +system.cpu1.commit.int_insts 17632180 # Number of committed integer instructions. +system.cpu1.commit.function_calls 461985 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12215165 61.81% 61.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 26577 0.13% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3993683 20.21% 82.17% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3521266 17.82% 99.99% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12236255 61.75% 61.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 27370 0.14% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 61.90% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.90% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.90% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.90% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4000808 20.19% 82.09% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3546708 17.90% 99.99% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction -system.cpu1.commit.bw_lim_events 379438 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 53719965 # The number of ROB reads -system.cpu1.rob.rob_writes 43510270 # The number of ROB writes -system.cpu1.timesIdled 58110 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 962680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5617725351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16085632 # Number of Instructions Simulated -system.cpu1.committedOps 19728885 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.169388 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.169388 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.460959 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.460959 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23317955 # number of integer regfile reads -system.cpu1.int_regfile_writes 13332838 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1403 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 19816226 # Class of committed instruction +system.cpu1.commit.bw_lim_events 379369 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 53607539 # The number of ROB reads +system.cpu1.rob.rob_writes 43609460 # The number of ROB writes +system.cpu1.timesIdled 58654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 976343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5617999605 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16123527 # Number of Instructions Simulated +system.cpu1.committedOps 19783370 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.154675 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.154675 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.464107 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.464107 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23404305 # number of integer regfile reads +system.cpu1.int_regfile_writes 13364979 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1400 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 74580678 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6681708 # number of cc regfile writes -system.cpu1.misc_regfile_reads 69976526 # number of misc regfile reads -system.cpu1.misc_regfile_writes 387406 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 185136 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.617373 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6737062 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 185477 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.322897 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89354157500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.617373 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915268 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915268 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14947542 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14947542 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3587773 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3587773 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2897885 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2897885 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49072 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49072 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78768 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78768 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70845 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70845 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6485658 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6485658 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6534730 # number of overall hits -system.cpu1.dcache.overall_hits::total 6534730 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 212319 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 212319 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 390908 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 390908 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29887 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 29887 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18355 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18355 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23465 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23465 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 603227 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 603227 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 633114 # number of overall misses -system.cpu1.dcache.overall_misses::total 633114 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3545506500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3545506500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9944995958 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9944995958 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362846000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 362846000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551070500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 551070500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 640500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 640500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13490502458 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13490502458 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13490502458 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13490502458 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3800092 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3800092 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3288793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3288793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78959 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 78959 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97123 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97123 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94310 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94310 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7088885 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7088885 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7167844 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7167844 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055872 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.055872 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118861 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.118861 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378513 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378513 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188987 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188987 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248807 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248807 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085095 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085095 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088327 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.088327 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 74742517 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6682824 # number of cc regfile writes +system.cpu1.misc_regfile_reads 68331723 # number of misc regfile reads +system.cpu1.misc_regfile_writes 381677 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 186538 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.297864 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6754124 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 186882 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.141116 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89307598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.297864 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920504 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920504 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.671875 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14996504 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14996504 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3592307 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3592307 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2912324 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2912324 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49253 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49253 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78431 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78431 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70573 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70573 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6504631 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6504631 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6553884 # number of overall hits +system.cpu1.dcache.overall_hits::total 6553884 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 213962 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 213962 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 393973 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 393973 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30075 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30075 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18449 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18449 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23608 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23608 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 607935 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 607935 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 638010 # number of overall misses +system.cpu1.dcache.overall_misses::total 638010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3561244000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3561244000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10027675956 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10027675956 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 364257500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 364257500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554259000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 554259000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 434000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 434000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13588919956 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13588919956 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13588919956 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13588919956 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3806269 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3806269 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3306297 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3306297 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79328 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79328 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96880 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96880 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94181 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94181 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7112566 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7112566 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7191894 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7191894 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056213 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.056213 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.119158 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.119158 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379122 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379122 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190431 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190431 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250666 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250666 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085473 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085473 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088712 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.088712 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16644.282630 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16644.282630 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.698423 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.698423 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19744.024066 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19744.024066 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23477.592342 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23477.592342 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1473013 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39225 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.552913 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 185136 # number of writebacks -system.cpu1.dcache.writebacks::total 185136 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 77580 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 77580 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 301933 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 301933 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13088 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13088 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 379513 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 379513 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 379513 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 379513 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134739 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 134739 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 88975 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 88975 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28539 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28539 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5267 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5267 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23465 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23465 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 223714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 223714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 252253 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 252253 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3386 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6126 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1970715500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1970715500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2395378969 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2395378969 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 480267000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 480267000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94406500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94406500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527620500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527620500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4366094469 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4366094469 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846361469 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4846361469 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 459425000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 459425000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 459425000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 459425000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035457 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035457 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027054 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027054 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054230 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054230 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248807 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248807 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031558 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031558 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035192 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035192 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14626.169854 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14626.169854 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26921.932779 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26921.932779 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16828.445285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22352.586964 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22352.586964 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21298.913741 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21298.913741 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 300 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1464130 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39463 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.677419 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.101335 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 186538 # number of writebacks +system.cpu1.dcache.writebacks::total 186538 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78472 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 78472 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 304164 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 304164 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13133 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13133 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 382636 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 382636 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 382636 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 382636 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 135490 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 135490 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89809 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89809 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28779 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28779 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5316 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5316 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23608 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23608 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254078 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254078 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2880 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5110 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973019500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1973019500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2438757966 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2438757966 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 489881500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 489881500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95317000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95317000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530661000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530661000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 424000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 424000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4411777466 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4411777466 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4901658966 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4901658966 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 386538000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 386538000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 386538000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 386538000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027163 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027163 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362785 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362785 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054872 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054872 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250666 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250666 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031676 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031676 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035328 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035328 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.104214 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14562.104214 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27154.939549 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27154.939549 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17022.186316 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17022.186316 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17930.210685 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17930.210685 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22478.015927 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22478.015927 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19212.304587 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19212.304587 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135683.697578 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 135683.697578 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 74995.919034 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 74995.919034 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 583486 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.437314 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7557735 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 583998 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.941371 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79127078000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.437314 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975464 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975464 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19581.877709 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19581.877709 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19291.945647 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19291.945647 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134214.583333 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134214.583333 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 75643.444227 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 75643.444227 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 594968 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.436901 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7527273 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 595480 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 12.640681 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79132209500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.436901 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975463 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975463 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16911139 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16911139 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7557735 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7557735 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7557735 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7557735 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7557735 # number of overall hits -system.cpu1.icache.overall_hits::total 7557735 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 605833 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 605833 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 605833 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 605833 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 605833 # number of overall misses -system.cpu1.icache.overall_misses::total 605833 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5683938295 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5683938295 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5683938295 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5683938295 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5683938295 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5683938295 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8163568 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8163568 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8163568 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8163568 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8163568 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8163568 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074212 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074212 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074212 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074212 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074212 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074212 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9382.021605 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9382.021605 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9382.021605 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9382.021605 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 514122 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41357 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.431318 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 583486 # number of writebacks -system.cpu1.icache.writebacks::total 583486 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21830 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 21830 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 21830 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 21830 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 21830 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 21830 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 584003 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 584003 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 584003 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 584003 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 584003 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 584003 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 16885432 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16885432 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 7527273 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7527273 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7527273 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7527273 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7527273 # number of overall hits +system.cpu1.icache.overall_hits::total 7527273 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 617701 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 617701 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 617701 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 617701 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 617701 # number of overall misses +system.cpu1.icache.overall_misses::total 617701 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5784933521 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5784933521 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5784933521 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5784933521 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5784933521 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5784933521 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8144974 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8144974 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8144974 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8144974 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8144974 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8144974 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.075838 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.075838 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.075838 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.075838 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.075838 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.075838 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9365.264944 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9365.264944 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9365.264944 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9365.264944 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 523604 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42411 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.345948 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 594968 # number of writebacks +system.cpu1.icache.writebacks::total 594968 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22217 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22217 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22217 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22217 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22217 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22217 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595484 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 595484 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 595484 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 595484 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 595484 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 595484 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5223422114 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5223422114 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5223422114 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5223422114 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5223422114 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5223422114 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9321999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9321999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9321999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9321999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071538 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071538 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8944.170003 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 192037 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 192612 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 514 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5318077800 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5318077800 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5318077800 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5318077800 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5318077800 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5318077800 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9663500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9663500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9663500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9663500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.073111 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.073111 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.073111 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8930.681261 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95678.217822 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95678.217822 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194116 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194726 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 546 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 57820 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43247 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14634.111672 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 688069 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 57318 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.004414 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59858 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 43575 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14594.735842 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 700816 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 57699 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 12.146068 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.708728 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.055002 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 436.823115 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.865694 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000715 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026662 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.893195 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 321 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 183 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14193.075757 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.827460 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.968470 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.864155 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.866277 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023673 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.890792 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 356 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13738 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 202 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 139 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8668 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3318 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019592 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27096059 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27096059 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16526 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5997 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 22523 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 112708 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 112708 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 643666 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 643666 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26963 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 26963 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 560151 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 560151 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97699 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 97699 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16526 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5997 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 560151 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 124662 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 707336 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16526 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5997 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 560151 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 124662 # number of overall hits -system.cpu1.l2cache.overall_hits::total 707336 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 498 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 789 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29191 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29191 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23465 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23465 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33482 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33482 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23849 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 23849 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70829 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 70829 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 498 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 291 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 23849 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104311 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 128949 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 498 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 291 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 23849 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104311 # number of overall misses -system.cpu1.l2cache.overall_misses::total 128949 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11142500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5993500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 17136000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12596500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 12596500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 19283000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 19283000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 603000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 603000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1436185500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1436185500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 937727500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 937727500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1638546999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1638546999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11142500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5993500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 937727500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3074732499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4029595999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11142500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5993500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 937727500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3074732499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4029595999 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17024 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6288 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 23312 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 112708 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 112708 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 643666 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 643666 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29191 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29191 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23465 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23465 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60445 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 60445 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 584000 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 584000 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168528 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 168528 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17024 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6288 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 584000 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 228973 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 836285 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17024 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6288 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 584000 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 228973 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 836285 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046279 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1740 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8639 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3359 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021729 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.838501 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 27539438 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 27539438 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17059 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6202 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 23261 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 113931 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 113931 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 655101 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 655101 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27113 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27113 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 571525 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 571525 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98074 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 98074 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17059 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6202 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 571525 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 125187 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 719973 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17059 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6202 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 571525 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 125187 # number of overall hits +system.cpu1.l2cache.overall_hits::total 719973 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 502 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 304 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 806 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29460 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29460 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23607 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33905 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33905 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23957 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 23957 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71492 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 71492 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 502 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 304 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 23957 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 105397 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 130160 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 502 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 304 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 23957 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 105397 # number of overall misses +system.cpu1.l2cache.overall_misses::total 130160 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10772500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6194000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 16966500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12496500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 12496500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18899500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18899500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 407499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 407499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1469375000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1469375000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 945511500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 945511500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1646741997 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1646741997 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10772500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6194000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 945511500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3116116997 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4078594997 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10772500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6194000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 945511500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3116116997 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4078594997 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17561 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6506 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 24067 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113931 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 113931 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 655101 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 655101 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29460 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29460 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23607 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23607 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61018 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61018 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 595482 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 595482 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 169566 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 169566 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17561 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6506 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 595482 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 230584 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 850133 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17561 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6506 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 595482 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 230584 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 850133 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046726 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.033490 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.553925 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.553925 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040837 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040837 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.420280 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.420280 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046279 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040837 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455560 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.154193 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046279 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040837 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455560 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.154193 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20596.219931 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21718.631179 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 431.519989 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 431.519989 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 821.777115 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 821.777115 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42894.256615 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42894.256615 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39319.363495 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39319.363495 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23133.843468 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23133.843468 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31249.532753 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31249.532753 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555656 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555656 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040231 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040231 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421618 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421618 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046726 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040231 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.457087 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.153105 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046726 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040231 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.457087 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.153105 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20375 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21050.248139 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 424.185336 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 424.185336 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 800.588808 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 800.588808 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 407499 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407499 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43338.003244 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43338.003244 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39467.024252 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39467.024252 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23033.933825 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23033.933825 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31335.241219 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31335.241219 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 817 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 30888 # number of writebacks -system.cpu1.l2cache.writebacks::total 30888 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 456 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 456 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 69 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 525 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 525 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 535 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 498 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 290 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 788 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 25130 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29191 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29191 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23465 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23465 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33026 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33026 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23840 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23840 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70760 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70760 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 498 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 290 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23840 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103786 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 128414 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 498 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 290 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23840 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103786 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 153544 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 799 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 31397 # number of writebacks +system.cpu1.l2cache.writebacks::total 31397 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 430 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 430 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 65 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 495 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 495 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 505 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 501 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 302 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 25004 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29460 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29460 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23607 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33475 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33475 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23950 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23950 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71427 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71427 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 501 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 302 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23950 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104902 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 129655 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 501 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 302 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23950 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104902 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 154659 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3487 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2981 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 6227 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4235000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12389500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1120294346 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 448208500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 448208500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351353500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351353500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 513000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 513000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1175287000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1175287000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 794529500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 794529500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1211572499 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1211572499 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4235000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 794529500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2386859499 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3193778499 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4235000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 794529500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2386859499 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4314072845 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8564000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 432303000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 440867000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8564000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 432303000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 440867000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033802 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5211 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4342500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12091000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1098165233 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453245500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453245500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353298500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353298500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 347499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 347499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1209651000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1209651000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 801689000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 801689000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1215836497 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1215836497 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4342500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 801689000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2425487497 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3239267497 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4342500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 801689000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2425487497 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4337432730 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8906000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 363460500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 372366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8906000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 363460500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 372366500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546381 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546381 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040822 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.419871 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.419871 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153553 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548609 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548609 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040220 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421234 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421234 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152511 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183602 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1644268 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 831312 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115055 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106415 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8640 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31394 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 822139 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 144852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 655914 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 29483 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30330 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71834 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 67721 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64923 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 584003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 271211 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 307 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1751691 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 836213 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14098 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37121 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2639123 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74720720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29257698 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68096 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 104071666 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 343275 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4808780 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1162877 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.125522 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.353024 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181923 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15057.285181 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43919.582187 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15385.115411 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15385.115411 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.836404 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.836404 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347499 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347499 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36135.952203 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36135.952203 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33473.444676 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17022.085444 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17022.085444 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24983.745301 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28045.136268 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126201.562500 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124913.284133 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 71127.299413 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 71457.781616 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1670520 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 844468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115035 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106284 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8751 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 31435 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 834833 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 146689 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 667575 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73183 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41990 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85875 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 595484 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 273707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 370 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1786136 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839744 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14453 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38068 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2678401 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76190416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29457424 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70244 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 105744108 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 346325 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4857548 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1179057 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.123952 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.351329 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1025550 88.19% 88.19% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 128687 11.07% 99.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8640 0.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1041662 88.35% 88.35% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 128644 10.91% 99.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8751 0.74% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1162877 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1604189995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1179057 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1629779992 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80522049 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80742792 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 876204799 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 893427297 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 375699214 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 378082159 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 7819481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 7957978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20111970 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20520473 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 59421 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59420 # Transaction distribution +system.iobus.trans_dist::WriteResp 59420 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2907,11 +2919,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71542 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2930,70 +2942,70 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40380000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 114000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 328000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 570500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 573500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6100500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6114001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33792000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33826000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187796551 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187862511 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.553749 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.554422 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255488373000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.553749 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909609 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909609 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255374847000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.554422 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909651 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909651 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -3002,14 +3014,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 40604377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 40604377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4366091174 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4366091174 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4406695551 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4406695551 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4406695551 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4406695551 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 39163375 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 39163375 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4357678136 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4357678136 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4396841511 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4396841511 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4396841511 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4396841511 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -3026,19 +3038,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 161128.480159 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120810.822212 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120810.822212 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 155410.218254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155410.218254 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120298.093419 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120298.093419 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120540.670879 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120540.670879 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 87 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.750000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 21.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3050,14 +3062,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 28004377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 28004377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2552566881 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2552566881 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2580571258 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2580571258 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2580571258 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2580571258 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 26563375 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 26563375 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2544616232 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2544616232 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2571179607 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2571179607 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2571179607 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2571179607 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3066,612 +3078,621 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137609 # number of replacements -system.l2c.tags.tagsinuse 65136.051895 # Cycle average of tags in use -system.l2c.tags.total_refs 548833 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202971 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.703997 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 87466496000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 5939.611941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.674941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8089.660546 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7047.830837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37514.795432 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.739703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.908322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1674.813935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2903.059558 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1945.895041 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.090631 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000239 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105410.218254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105410.218254 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70246.693684 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70246.693684 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137305 # number of replacements +system.l2c.tags.tagsinuse 65135.020938 # Cycle average of tags in use +system.l2c.tags.total_refs 548309 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202660 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.705561 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 87489923000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6043.335191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.875782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.068168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8238.246856 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6901.068519 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37215.588563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.685294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909748 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1676.975803 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3036.574639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2001.692374 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.092214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000258 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.123438 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.107541 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.125706 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105302 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025556 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044297 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993897 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33502 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31839 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26990 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4972 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 26706 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.511200 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.485825 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6298618 # Number of tag accesses -system.l2c.tags.data_accesses 6298618 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 261626 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 261626 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 41310 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4699 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 46009 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2684 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4894 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5320 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 248 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 107 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 50964 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 57616 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46197 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 67 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21124 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11550 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4807 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 192709 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 50964 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 61594 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 67 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12892 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4807 # number of demand (read+write) hits -system.l2c.demand_hits::total 198029 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 248 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 107 # number of overall hits -system.l2c.overall_hits::cpu0.inst 50964 # number of overall hits -system.l2c.overall_hits::cpu0.data 61594 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46197 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 67 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21124 # number of overall hits -system.l2c.overall_hits::cpu1.data 12892 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4807 # number of overall hits -system.l2c.overall_hits::total 198029 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 543 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 291 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 834 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 92 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 104 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 196 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11177 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8193 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19370 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 29 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19953 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9351 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131846 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 4 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.025589 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.046334 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030543 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993882 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33214 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6015 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27014 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27124 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.506805 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.490097 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6291007 # Number of tag accesses +system.l2c.tags.data_accesses 6291007 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 261222 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 261222 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 41572 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4769 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 46341 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2758 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2241 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4999 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3976 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1584 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5560 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 265 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 106 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 50549 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 57222 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46457 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 49 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 21200 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11593 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4929 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 192388 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 50549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 61198 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46457 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21200 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13177 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4929 # number of demand (read+write) hits +system.l2c.demand_hits::total 197948 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 265 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 106 # number of overall hits +system.l2c.overall_hits::cpu0.inst 50549 # number of overall hits +system.l2c.overall_hits::cpu0.data 61198 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46457 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21200 # number of overall hits +system.l2c.overall_hits::cpu1.data 13177 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4929 # number of overall hits +system.l2c.overall_hits::total 197948 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 273 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 798 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 53 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 86 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 139 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11064 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8230 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19294 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19971 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9413 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2712 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 981 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6675 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 171555 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19953 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20528 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 131846 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2746 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 945 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 171189 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 26 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 19971 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20477 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2712 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9174 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6675 # number of demand (read+write) misses -system.l2c.demand_misses::total 190925 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 19953 # number of overall misses -system.l2c.overall_misses::cpu0.data 20528 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 131846 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2746 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) misses +system.l2c.demand_misses::total 190483 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 26 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 19971 # number of overall misses +system.l2c.overall_misses::cpu0.data 20477 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 131312 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2712 # number of overall misses -system.l2c.overall_misses::cpu1.data 9174 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6675 # number of overall misses -system.l2c.overall_misses::total 190925 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 8706000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 803000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9509000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 672000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 510500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1182500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1649911000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 752041000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2401952000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3955500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2094281000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1081713000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 903500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 288810000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 120918000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 21127246053 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 3955500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 249000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2094281000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2731624000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 903500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 288810000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 872959000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 23529198053 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 3955500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 249000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2094281000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2731624000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 903500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 288810000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 872959000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of overall miss cycles -system.l2c.overall_miss_latency::total 23529198053 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 261626 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 261626 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 41853 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4990 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46843 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2776 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2314 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5090 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15155 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9535 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24690 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 277 # number of ReadSharedReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.inst 2746 # number of overall misses +system.l2c.overall_misses::cpu1.data 9175 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6765 # number of overall misses +system.l2c.overall_misses::total 190483 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 10093000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 519000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 709500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 365000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1074500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1647098500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 779902000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2427000500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4012500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 353000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2097163000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106791000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 538500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 90000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 295133500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 115926000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 20927340320 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 4012500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 353000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2097163000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2753889500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 538500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 90000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 295133500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 895828000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 23354340820 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 4012500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 353000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 2097163000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2753889500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 538500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 90000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 295133500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 895828000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of overall miss cycles +system.l2c.overall_miss_latency::total 23354340820 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 261222 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 261222 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 42097 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 47139 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2811 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2327 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 5138 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15040 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 291 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 110 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 70917 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 66967 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 178043 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 71 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 23836 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12531 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11482 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 364264 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 277 # number of demand (read+write) accesses +system.l2c.ReadSharedReq_accesses::cpu0.inst 70520 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 66635 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177769 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 55 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 19 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 23946 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12538 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11694 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 363577 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 291 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 70917 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 82122 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 178043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 71 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 23836 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 22066 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11482 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 388954 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 277 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 70520 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 81675 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177769 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 55 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 23946 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 22352 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11694 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 388431 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 291 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 70917 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 82122 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 178043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 71 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 23836 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 22066 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11482 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 388954 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012974 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.058317 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.017804 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033141 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.044944 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.038507 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.737512 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.859255 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.784528 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027273 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.281357 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.139636 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.113777 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078286 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.470963 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.027273 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.281357 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.249970 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.113777 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.415753 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.490868 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.027273 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.281357 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.249970 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.113777 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.415753 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.490868 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16033.149171 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2759.450172 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 11401.678657 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7304.347826 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4908.653846 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6033.163265 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147616.623423 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 91790.674966 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 124003.717088 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 104960.707663 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115678.857876 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 225875 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106493.362832 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123259.938838 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 123151.444452 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 123237.910452 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 123237.910452 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 225 # number of cycles access was blocked +system.l2c.overall_accesses::cpu0.inst 70520 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 81675 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177769 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 55 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 23946 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 22352 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11694 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 388431 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012471 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.054145 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.016929 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018855 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.036957 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.027053 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.735638 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.838598 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.776294 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036364 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.283196 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.141262 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.052632 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.114675 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.075371 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.470847 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.036364 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.283196 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.250713 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.052632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.114675 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.410478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.490391 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.036364 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.283196 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.250713 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.052632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.114675 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.410478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.490391 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19224.761905 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1901.098901 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13298.245614 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13386.792453 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4244.186047 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 7730.215827 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148870.074114 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94763.304982 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 125790.427076 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88250 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 105010.415102 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 117581.111229 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 90000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 107477.603787 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 122673.015873 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 122246.992038 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 122605.906144 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 122605.906144 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 101341 # number of writebacks -system.l2c.writebacks::total 101341 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4056 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4056 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 543 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 291 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 834 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 92 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 104 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 196 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11177 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8193 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19370 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19952 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9351 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131846 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadSharedReq MSHR misses +system.l2c.writebacks::writebacks 100899 # number of writebacks +system.l2c.writebacks::total 100899 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 11 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 4091 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 4091 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 525 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 273 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 798 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 53 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 86 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 139 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11064 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8230 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19294 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 26 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19969 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9413 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2712 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 981 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 171554 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 19952 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20528 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131846 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2738 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 944 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 171178 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 26 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 19969 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2712 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2738 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 9174 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190924 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 19952 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20528 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131846 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 190472 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 26 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 19969 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2712 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2738 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 9174 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190924 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 190472 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3383 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38274 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31197 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2877 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 37994 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30912 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6123 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69471 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12087000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6019500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 18106500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2426500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2307500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4734000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1538140501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 670111000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2208251501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 219000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1894738504 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 988203000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 863500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 261689501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111108000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19411677070 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1894738504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2526343501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 863500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 261689501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 781219000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21619928571 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1894738504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2526343501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 863500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 261689501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 781219000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21619928571 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5107 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 68906 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11977000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6297000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 18274000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1386000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1952500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3338500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1536458500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 697602000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2234060500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 313000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1897400002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1012660501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 478500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 267162500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 106122500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19214528830 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 313000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1897400002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2549119001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 478500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 267162500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 803724500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21448589330 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 313000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1897400002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2549119001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 478500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 267162500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 803724500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21448589330 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5797437001 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6745000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 371342000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6386465501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5849372000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7087000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311625000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6379025500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5797437001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6745000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 371342000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6386465501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5849372000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7087000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 311625000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6379025500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012974 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.058317 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.017804 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033141 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.044944 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038507 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737512 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.859255 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.784528 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139636 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078286 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470961 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.490865 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.490865 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26375 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012471 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.054145 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.016929 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018855 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.036957 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.027053 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735638 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.838598 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.776294 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.141262 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.075291 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470816 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.490363 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.490363 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22813.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23065.934066 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22899.749373 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26150.943396 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22703.488372 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24017.985612 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138870.074114 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84763.304982 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 115790.427076 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 107581.058217 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 112417.902542 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112248.821870 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182747.188203 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108315.954119 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167895.601937 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 504773 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 283620 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96381.150107 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 61019.189348 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92575.762633 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 504615 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 283930 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38274 # Transaction distribution -system.membus.trans_dist::ReadResp 210079 # Transaction distribution -system.membus.trans_dist::WriteReq 31197 # Transaction distribution -system.membus.trans_dist::WriteResp 31197 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137547 # Transaction distribution -system.membus.trans_dist::CleanEvict 17007 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64594 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38710 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37994 # Transaction distribution +system.membus.trans_dist::ReadResp 209423 # Transaction distribution +system.membus.trans_dist::WriteReq 30912 # Transaction distribution +system.membus.trans_dist::WriteResp 30912 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137105 # Transaction distribution +system.membus.trans_dist::CleanEvict 16916 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65086 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38844 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 38808 # Transaction distribution -system.membus.trans_dist::ReadExResp 19352 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171806 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 38910 # Transaction distribution +system.membus.trans_dist::ReadExResp 19275 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171430 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 4600 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 761276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 637823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 759513 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834225 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 832462 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18751880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18944702 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18694600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18885164 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21262846 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122284 # Total snoops (count) +system.membus.pkt_size::total 21203308 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 127782 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 419616 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012440 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110839 # Request fanout histogram +system.membus.snoop_fanout::samples 419404 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012453 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110898 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 414396 98.76% 98.76% # Request fanout histogram -system.membus.snoop_fanout::1 5220 1.24% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414181 98.75% 98.75% # Request fanout histogram +system.membus.snoop_fanout::1 5223 1.25% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 419616 # Request fanout histogram -system.membus.reqLayer0.occupancy 81572000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419404 # Request fanout histogram +system.membus.reqLayer0.occupancy 81639999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12355500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11433500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 987789803 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 984876925 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1102143190 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1099184232 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1335877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 7225285 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3703,81 +3724,82 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1044068 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 554075 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 185190 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28829 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27647 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38277 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 522605 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31197 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31197 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 362967 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 130325 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 110585 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43604 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 154189 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50073 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50073 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 484331 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4646 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1303151 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320962 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1624113 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36235416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5679078 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41914494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 390245 # Total snoops (count) -system.toL2Bus.snoopTraffic 15796172 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 900374 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.402074 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.492987 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1044885 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 541195 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 200373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29262 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27938 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1324 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 37997 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 522881 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30912 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30912 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 362121 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129726 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111408 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43843 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155251 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50410 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50410 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 484889 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4647 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3467 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1304964 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322117 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1627081 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36107224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5745684 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41852908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 395541 # Total snoops (count) +system.toL2Bus.snoopTraffic 15858252 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 901455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.406700 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494199 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 539539 59.92% 59.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 359653 39.94% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1182 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 536157 59.48% 59.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 363974 40.38% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1324 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 900374 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 896925065 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 901455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 896599840 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2176474 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 692605391 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 692364962 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 242340870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 244002323 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2732 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 31402aa9f..2b2b80402 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.829113 # Number of seconds simulated -sim_ticks 2829112944500 # Number of ticks simulated -final_tick 2829112944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.829116 # Number of seconds simulated +sim_ticks 2829116273500 # Number of ticks simulated +final_tick 2829116273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178657 # Simulator instruction rate (inst/s) -host_op_rate 216701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4466095842 # Simulator tick rate (ticks/s) -host_mem_usage 588180 # Number of bytes of host memory used -host_seconds 633.46 # Real time elapsed on the host -sim_insts 113173049 # Number of instructions simulated -sim_ops 137272583 # Number of ops (including micro ops) simulated +host_inst_rate 175307 # Simulator instruction rate (inst/s) +host_op_rate 212638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4382427767 # Simulator tick rate (ticks/s) +host_mem_usage 587848 # Number of bytes of host memory used +host_seconds 645.56 # Real time elapsed on the host +sim_insts 113171321 # Number of instructions simulated +sim_ops 137270537 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 896 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1316512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9472808 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10791880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1316512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1316512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8091648 # Number of bytes written to this memory +system.physmem.bytes_read::total 10791176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8091200 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8109172 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8108724 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148533 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171395 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126432 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171384 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126425 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 130813 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 317 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 130806 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 339 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 465344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3348422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 465163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3348328 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3814581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 465344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2860136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3814327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 465163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2859974 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2866330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2860136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2866169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2859974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 339 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 465344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3354616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 465163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3354522 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6680911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171396 # Number of read requests accepted -system.physmem.writeReqs 130813 # Number of write requests accepted -system.physmem.readBursts 171396 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 130813 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10959744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue -system.physmem.bytesWritten 8121728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10791944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8109172 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6680496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171385 # Number of read requests accepted +system.physmem.writeReqs 130806 # Number of write requests accepted +system.physmem.readBursts 171385 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 130806 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10959936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 8121280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10791240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8108724 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10680 # Per bank write bursts +system.physmem.perBankRdBursts::0 10685 # Per bank write bursts system.physmem.perBankRdBursts::1 10044 # Per bank write bursts -system.physmem.perBankRdBursts::2 10837 # Per bank write bursts -system.physmem.perBankRdBursts::3 10904 # Per bank write bursts -system.physmem.perBankRdBursts::4 13724 # Per bank write bursts -system.physmem.perBankRdBursts::5 10680 # Per bank write bursts -system.physmem.perBankRdBursts::6 11438 # Per bank write bursts +system.physmem.perBankRdBursts::2 10839 # Per bank write bursts +system.physmem.perBankRdBursts::3 10919 # Per bank write bursts +system.physmem.perBankRdBursts::4 13721 # Per bank write bursts +system.physmem.perBankRdBursts::5 10679 # Per bank write bursts +system.physmem.perBankRdBursts::6 11440 # Per bank write bursts system.physmem.perBankRdBursts::7 11401 # Per bank write bursts -system.physmem.perBankRdBursts::8 10103 # Per bank write bursts -system.physmem.perBankRdBursts::9 10404 # Per bank write bursts +system.physmem.perBankRdBursts::8 10106 # Per bank write bursts +system.physmem.perBankRdBursts::9 10397 # Per bank write bursts system.physmem.perBankRdBursts::10 10359 # Per bank write bursts -system.physmem.perBankRdBursts::11 9493 # Per bank write bursts -system.physmem.perBankRdBursts::12 10229 # Per bank write bursts -system.physmem.perBankRdBursts::13 11052 # Per bank write bursts -system.physmem.perBankRdBursts::14 10015 # Per bank write bursts -system.physmem.perBankRdBursts::15 9883 # Per bank write bursts -system.physmem.perBankWrBursts::0 8063 # Per bank write bursts -system.physmem.perBankWrBursts::1 7694 # Per bank write bursts +system.physmem.perBankRdBursts::11 9487 # Per bank write bursts +system.physmem.perBankRdBursts::12 10224 # Per bank write bursts +system.physmem.perBankRdBursts::13 11051 # Per bank write bursts +system.physmem.perBankRdBursts::14 10016 # Per bank write bursts +system.physmem.perBankRdBursts::15 9881 # Per bank write bursts +system.physmem.perBankWrBursts::0 8064 # Per bank write bursts +system.physmem.perBankWrBursts::1 7693 # Per bank write bursts system.physmem.perBankWrBursts::2 8368 # Per bank write bursts -system.physmem.perBankWrBursts::3 8157 # Per bank write bursts -system.physmem.perBankWrBursts::4 8127 # Per bank write bursts +system.physmem.perBankWrBursts::3 8158 # Per bank write bursts +system.physmem.perBankWrBursts::4 8126 # Per bank write bursts system.physmem.perBankWrBursts::5 8035 # Per bank write bursts -system.physmem.perBankWrBursts::6 8542 # Per bank write bursts +system.physmem.perBankWrBursts::6 8543 # Per bank write bursts system.physmem.perBankWrBursts::7 8476 # Per bank write bursts -system.physmem.perBankWrBursts::8 7684 # Per bank write bursts -system.physmem.perBankWrBursts::9 7982 # Per bank write bursts -system.physmem.perBankWrBursts::10 7772 # Per bank write bursts -system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::8 7685 # Per bank write bursts +system.physmem.perBankWrBursts::9 7978 # Per bank write bursts +system.physmem.perBankWrBursts::10 7774 # Per bank write bursts +system.physmem.perBankWrBursts::11 7091 # Per bank write bursts system.physmem.perBankWrBursts::12 7777 # Per bank write bursts -system.physmem.perBankWrBursts::13 8429 # Per bank write bursts -system.physmem.perBankWrBursts::14 7462 # Per bank write bursts -system.physmem.perBankWrBursts::15 7237 # Per bank write bursts +system.physmem.perBankWrBursts::13 8428 # Per bank write bursts +system.physmem.perBankWrBursts::14 7463 # Per bank write bursts +system.physmem.perBankWrBursts::15 7236 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 78 # Number of times write queue was full causing retry -system.physmem.totGap 2829112709500 # Total gap between requests +system.physmem.numWrRetry 64 # Number of times write queue was full causing retry +system.physmem.totGap 2829116038500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 3002 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 167838 # Read request sizes (log2) +system.physmem.readPktSize::6 167827 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126432 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 866 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126425 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 860 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,126 +160,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 207 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.483382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.687105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.840241 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22553 36.82% 36.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14650 23.91% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6334 10.34% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3752 6.12% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2675 4.37% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1648 2.69% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1058 1.73% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1036 1.69% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7554 12.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6323 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.072592 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 535.871052 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6321 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 176 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.408036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.010622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.226456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22407 36.57% 36.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14885 24.29% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6282 10.25% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3692 6.03% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2681 4.38% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1694 2.76% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.85% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 990 1.62% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7507 12.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61274 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6334 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.026050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 535.405637 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6332 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6323 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.069904 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.255220 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.875839 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5596 88.50% 88.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 1.30% 89.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 0.84% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 0.59% 91.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 252 3.99% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 36 0.57% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.14% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.11% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 139 2.20% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 10 0.16% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 12 0.19% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.24% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6334 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.033944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.251538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.603630 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5594 88.32% 88.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 89 1.41% 89.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.68% 90.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 45 0.71% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 260 4.10% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.33% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.35% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.16% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.17% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 137 2.16% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 10 0.16% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.09% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.21% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6323 # Writes before turning the bus around for reads -system.physmem.totQLat 4766161750 # Total ticks spent queuing -system.physmem.totMemAccLat 7977024250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 856230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27832.09 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6334 # Writes before turning the bus around for reads +system.physmem.totQLat 4767396000 # Total ticks spent queuing +system.physmem.totMemAccLat 7978314750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 856245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27838.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46581.98 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46588.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s @@ -289,52 +289,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.57 # Average write queue length when enqueuing -system.physmem.readRowHits 141751 # Number of row buffer hits during reads -system.physmem.writeRowHits 95137 # Number of row buffer hits during writes +system.physmem.avgWrQLen 27.69 # Average write queue length when enqueuing +system.physmem.readRowHits 141756 # Number of row buffer hits during reads +system.physmem.writeRowHits 95114 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes -system.physmem.avgGap 9361444.26 # Average gap between requests -system.physmem.pageHitRate 79.45 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229201140 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121823295 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640515120 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 341711640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5262547680.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4339877970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 323354400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10814226390 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7334392800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667253476395 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 696663805260 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.248141 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2818581671250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 598120000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2237496000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2775932271000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 19100075750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7529604250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23715377500 # Time in different power states -system.physmem_1.actEnergy 208195260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 110658405 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 582181320 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 320716800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5105199840.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4092887280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 324388800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10096669920 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 7288782240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667807505910 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 695939317005 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.992058 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2819287837500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 611681500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2171134000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778164795750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 18981177000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7042291500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22141864750 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.physmem.writeRowHitRate 74.94 # Row buffer hit rate for writes +system.physmem.avgGap 9362012.89 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121660110 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640657920 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 341716860 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5259474480.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4230417450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 318207360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10873180350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7365080640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667265125080 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 696646226220 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.241638 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2818840383250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 582284750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2236202000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2775981781500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 19179858500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7291367000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23844779750 # Time in different power states +system.physmem_1.actEnergy 208602240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110874720 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 582059940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 320675040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5116263360.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4098436230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 317114880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10121131470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 7324658880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667774632810 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 695976520350 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.004919 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2819298070500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 592691750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2175820000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778027972250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 19074668750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7049691250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22195429500 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -347,30 +347,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46887151 # Number of BP lookups -system.cpu.branchPred.condPredicted 24003532 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1173792 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29506695 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13539046 # Number of BTB hits +system.cpu.branchPred.lookups 46888279 # Number of BP lookups +system.cpu.branchPred.condPredicted 24003428 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1174058 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29505954 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13539674 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.884658 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754270 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34776 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7941183 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7796256 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 144927 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60295 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.887938 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754876 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34853 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7941192 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7796111 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145081 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60202 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,75 +400,75 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 71256 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71256 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29049 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23358 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 18849 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52407 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 389.146488 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2289.126746 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50564 96.48% 96.48% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 708 1.35% 97.83% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 582 1.11% 98.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 319 0.61% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 71258 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71258 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29064 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23380 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 18814 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52444 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 391.093357 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2302.538664 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50603 96.49% 96.49% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 703 1.34% 97.83% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 574 1.09% 98.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 328 0.63% 99.55% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52407 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16824 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9444.513790 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7664.409790 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6506.438101 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-8191 8278 49.20% 49.20% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::8192-16383 6918 41.12% 90.32% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-24575 1373 8.16% 98.48% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::24576-32767 165 0.98% 99.47% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-40959 22 0.13% 99.60% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 52444 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16825 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9444.665676 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7665.862074 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6497.692830 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-8191 8271 49.16% 49.16% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::8192-16383 6932 41.20% 90.36% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-24575 1364 8.11% 98.47% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::24576-32767 166 0.99% 99.45% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-40959 23 0.14% 99.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::40960-49151 60 0.36% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-106495 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16824 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 118987489224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.630928 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.488775 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 118941247224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 32120500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6765500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4407000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 968000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 470000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 338000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::total 16825 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 118990825724 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.630270 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.488920 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 118944532224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 32222000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6760000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4376000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 965500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 468000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1159500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 331000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 118987489224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71256 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 118990825724 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6321 82.36% 82.36% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1354 17.64% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7675 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71258 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71256 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71258 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7675 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7675 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25423703 # DTB read hits -system.cpu.dtb.read_misses 61573 # DTB read misses -system.cpu.dtb.write_hits 19869711 # DTB write hits -system.cpu.dtb.write_misses 9683 # DTB write misses +system.cpu.dtb.read_hits 25423698 # DTB read hits +system.cpu.dtb.read_misses 61603 # DTB read misses +system.cpu.dtb.write_hits 19869004 # DTB write hits +system.cpu.dtb.write_misses 9655 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID @@ -477,14 +477,14 @@ system.cpu.dtb.flush_entries 4259 # Nu system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1309 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25485276 # DTB read accesses -system.cpu.dtb.write_accesses 19879394 # DTB write accesses +system.cpu.dtb.perms_faults 1308 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25485301 # DTB read accesses +system.cpu.dtb.write_accesses 19878659 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45293414 # DTB hits -system.cpu.dtb.misses 71256 # DTB misses -system.cpu.dtb.accesses 45364670 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45292702 # DTB hits +system.cpu.dtb.misses 71258 # DTB misses +system.cpu.dtb.accesses 45363960 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,51 +514,51 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12694 # Table walker walks requested -system.cpu.itb.walker.walksShort 12694 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3385 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7744 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1565 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11129 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 587.519094 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2554.039533 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10635 95.56% 95.56% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 121 1.09% 96.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.00% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 105 0.94% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 19 0.17% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 20 0.18% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12656 # Table walker walks requested +system.cpu.itb.walker.walksShort 12656 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3345 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1571 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11085 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 575.732972 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2511.318158 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10605 95.67% 95.67% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 108 0.97% 96.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.01% 98.66% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 110 0.99% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 16 0.14% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 18 0.16% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11129 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 4883 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9054.884292 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7027.204830 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 11165.478993 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 4881 99.96% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11085 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4896 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9060.763889 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7035.829304 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 11150.467524 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 4894 99.96% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 4883 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 24497265712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.701353 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.457724 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 7316690500 29.87% 29.87% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 17179912712 70.13% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 662500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 24497265712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2983 89.90% 89.90% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.10% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3318 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 4896 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24500602212 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.693564 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.461068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 7508480500 30.65% 30.65% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 16991502712 69.35% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 619000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24500602212 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2990 89.92% 89.92% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3325 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12694 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12694 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12656 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12656 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3318 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3318 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16012 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65985862 # ITB inst hits -system.cpu.itb.inst_misses 12694 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3325 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3325 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15981 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 65983065 # ITB inst hits +system.cpu.itb.inst_misses 12656 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -567,113 +567,113 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3015 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3022 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2167 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2179 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 65998556 # ITB inst accesses -system.cpu.itb.hits 65985862 # DTB hits -system.cpu.itb.misses 12694 # DTB misses -system.cpu.itb.accesses 65998556 # DTB accesses -system.cpu.numPwrStateTransitions 6076 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887100825.703094 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17420756349.556362 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 65995721 # ITB inst accesses +system.cpu.itb.hits 65983065 # DTB hits +system.cpu.itb.misses 12656 # DTB misses +system.cpu.itb.accesses 65995721 # DTB accesses +system.cpu.numPwrStateTransitions 6078 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3039 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886806915.729845 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17417893662.159683 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 134100636014 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012308486 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 268201326 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499972056544 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3039 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 134110056597 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695006216903 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 268220171 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 105037035 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 183958233 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46887151 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33089572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151917777 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6065436 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 178887 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338530 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 869885 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 153 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65984793 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 962400 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5953 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 261383837 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858435 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.227931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105042564 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 183946336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46888279 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33090661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151947545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6066122 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 177459 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8717 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 332750 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 861386 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 140 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65981974 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 958405 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5944 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261403622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.227883 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 162469808 62.16% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29156945 11.15% 73.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14047249 5.37% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55709835 21.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 162493227 62.16% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29157587 11.15% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14046843 5.37% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55705965 21.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 261383837 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.174821 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.685896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78154489 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 112430645 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64386105 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3839531 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2573067 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3403885 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157074107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3510025 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2573067 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83905287 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11250556 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76371084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62477293 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24806550 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146503885 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 915767 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 476463 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65809 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19068 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22053632 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150297963 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 677315873 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164027698 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11061 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141834071 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8463886 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844043 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2648878 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13862484 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26350148 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21217553 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1695311 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2061783 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143296271 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143117357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 261040 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8140399 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14276109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121662 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 261383837 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.547537 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.874444 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261403622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174813 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.685804 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78158537 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112446013 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64386093 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3839619 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2573360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3404101 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157070559 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3511367 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2573360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83910500 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11255138 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76381178 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62476128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24807318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146500137 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 914744 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 477372 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65897 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19059 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22053744 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150295383 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677299800 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164022340 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11055 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141831816 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8463561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844179 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649010 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13862871 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26349559 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21216979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1695969 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2055276 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143294681 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116741 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143114526 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260917 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8140881 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14283010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261403622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.547485 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.874392 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 173081384 66.22% 66.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45405843 17.37% 83.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31801280 12.17% 95.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10272399 3.93% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 822898 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 173098069 66.22% 66.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45413284 17.37% 83.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31798683 12.16% 95.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10270501 3.93% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 823052 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -681,9 +681,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 261383837 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261403622 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7335509 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7334511 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available @@ -714,135 +714,135 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5619374 25.11% 57.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9416245 42.07% 99.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5619720 25.11% 57.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9419018 42.08% 99.95% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8750 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8747 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95907816 67.01% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114378 0.08% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8550 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95906474 67.01% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114332 0.08% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8541 0.01% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26137714 18.26% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20934166 14.63% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26136950 18.26% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20933494 14.63% 99.99% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 9688 0.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 9690 0.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143117357 # Type of FU issued -system.cpu.iq.rate 0.533619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22382313 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 570225949 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153558624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140063898 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35955 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13316 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143114526 # Type of FU issued +system.cpu.iq.rate 0.533571 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22384431 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156409 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 570242068 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153557534 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140061190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35954 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13312 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165473779 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23554 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 325086 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165473068 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23552 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 325058 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1430934 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 704 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18603 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 620075 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1430930 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 739 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18590 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 619959 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88534 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6404 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88583 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2573067 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1155549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 418674 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145593643 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2573360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1161160 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 410961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145591536 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26350148 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21217553 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1093742 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17678 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 382838 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18603 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 276771 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 470806 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 747577 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142219738 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25746846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 826473 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26349559 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21216979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093729 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17740 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 375076 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18590 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 276726 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471114 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 747840 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142217911 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25746602 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 825466 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180657 # number of nop insts executed -system.cpu.iew.exec_refs 46578356 # number of memory reference insts executed -system.cpu.iew.exec_branches 26518178 # Number of branches executed -system.cpu.iew.exec_stores 20831510 # Number of stores executed -system.cpu.iew.exec_rate 0.530272 # Inst execution rate -system.cpu.iew.wb_sent 141851208 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140075398 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63278837 # num instructions producing a value -system.cpu.iew.wb_consumers 95827539 # num instructions consuming a value -system.cpu.iew.wb_rate 0.522277 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660341 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7356149 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995053 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 714141 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258490005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.132637 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180114 # number of nop insts executed +system.cpu.iew.exec_refs 46577390 # number of memory reference insts executed +system.cpu.iew.exec_branches 26518344 # Number of branches executed +system.cpu.iew.exec_stores 20830788 # Number of stores executed +system.cpu.iew.exec_rate 0.530228 # Inst execution rate +system.cpu.iew.wb_sent 141848584 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140072690 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63277897 # num instructions producing a value +system.cpu.iew.wb_consumers 95827474 # num instructions consuming a value +system.cpu.iew.wb_rate 0.522230 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660331 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7357031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995000 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 714357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258509266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.132560 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 184915208 71.54% 71.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43409459 16.79% 88.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15465173 5.98% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4364887 1.69% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6512039 2.52% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1543037 0.60% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 797927 0.31% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 416081 0.16% 99.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1066194 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 184931767 71.54% 71.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43412717 16.79% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15465745 5.98% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4363425 1.69% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6516677 2.52% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1538620 0.60% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 797794 0.31% 99.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 415780 0.16% 99.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1066741 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258490005 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113327954 # Number of instructions committed -system.cpu.commit.committedOps 137427488 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258509266 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113326226 # Number of instructions committed +system.cpu.commit.committedOps 137425442 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45516692 # Number of memory references committed -system.cpu.commit.loads 24919214 # Number of loads committed -system.cpu.commit.membars 814556 # Number of memory barriers committed -system.cpu.commit.branches 26054279 # Number of branches committed +system.cpu.commit.refs 45515649 # Number of memory references committed +system.cpu.commit.loads 24918629 # Number of loads committed +system.cpu.commit.membars 814537 # Number of memory barriers committed +system.cpu.commit.branches 26054301 # Number of branches committed system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120246700 # Number of committed integer instructions. -system.cpu.commit.function_calls 4895002 # Number of function calls committed. +system.cpu.commit.int_insts 120244809 # Number of committed integer instructions. +system.cpu.commit.function_calls 4895095 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91789332 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112915 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91788341 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112911 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -868,43 +868,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8541 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916506 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20588698 14.98% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24915921 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20588240 14.98% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137427488 # Class of committed instruction -system.cpu.commit.bw_lim_events 1066194 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 379949809 # The number of ROB reads -system.cpu.rob.rob_writes 292448043 # The number of ROB writes -system.cpu.timesIdled 895006 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6817489 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5390024564 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113173049 # Number of Instructions Simulated -system.cpu.committedOps 137272583 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.369834 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.369834 # CPI: Total CPI of All Threads -system.cpu.ipc 0.421971 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.421971 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155600043 # number of integer regfile reads -system.cpu.int_regfile_writes 88544133 # number of integer regfile writes -system.cpu.fp_regfile_reads 9688 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137425442 # Class of committed instruction +system.cpu.commit.bw_lim_events 1066741 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 379966373 # The number of ROB reads +system.cpu.rob.rob_writes 292446245 # The number of ROB writes +system.cpu.timesIdled 894795 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6816549 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5390012377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113171321 # Number of Instructions Simulated +system.cpu.committedOps 137270537 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.370037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.370037 # CPI: Total CPI of All Threads +system.cpu.ipc 0.421934 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.421934 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155596425 # number of integer regfile reads +system.cpu.int_regfile_writes 88542209 # number of integer regfile writes +system.cpu.fp_regfile_reads 9690 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502437138 # number of cc regfile reads -system.cpu.cc_regfile_writes 53153343 # number of cc regfile writes -system.cpu.misc_regfile_reads 452546223 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521066 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 835143 # number of replacements +system.cpu.cc_regfile_reads 502428467 # number of cc regfile reads +system.cpu.cc_regfile_writes 53152553 # number of cc regfile writes +system.cpu.misc_regfile_reads 452520947 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521018 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 835071 # number of replacements system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40081033 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 835655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.963613 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40080644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 835583 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.967280 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy @@ -914,463 +914,463 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179197279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179197279 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23277440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23277440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15552456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15552456 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346215 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346215 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441873 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460172 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460172 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38829896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38829896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39176111 # number of overall hits -system.cpu.dcache.overall_hits::total 39176111 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 703989 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 703989 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3604729 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3604729 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 176925 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 176925 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26598 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26598 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179195359 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179195359 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23277723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23277723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15551809 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15551809 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346190 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346190 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441882 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441882 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460162 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460162 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38829532 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38829532 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39175722 # number of overall hits +system.cpu.dcache.overall_hits::total 39175722 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 703752 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 703752 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3604950 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3604950 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 176883 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 176883 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26584 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26584 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4308718 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4308718 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4485643 # number of overall misses -system.cpu.dcache.overall_misses::total 4485643 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11027261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11027261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 167170360202 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 167170360202 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 370603000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 370603000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4308702 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4308702 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4485585 # number of overall misses +system.cpu.dcache.overall_misses::total 4485585 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11028419500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11028419500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 167321691201 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 167321691201 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 369201500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 178197621202 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 178197621202 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 178197621202 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 178197621202 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23981429 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23981429 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19157185 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19157185 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523140 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523140 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460176 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460176 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43138614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43138614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43661754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43661754 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029356 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029356 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188166 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338198 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338198 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 178350110701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 178350110701 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 178350110701 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 178350110701 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23981475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23981475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19156759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19156759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523073 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523073 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460166 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460166 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43138234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43138234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43661307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43661307 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029346 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029346 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188182 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188182 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338161 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338161 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056747 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056747 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15663.967761 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15663.967761 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46375.292068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46375.292068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13933.491240 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13933.491240 # average LoadLockedReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15670.889035 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15670.889035 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46414.427718 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46414.427718 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13888.109389 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13888.109389 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41357.457416 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41357.457416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39726.215662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39726.215662 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 633494 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41393.002046 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41393.002046 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39760.724789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39760.724789 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 631534 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7037 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.023305 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.064746 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 694028 # number of writebacks -system.cpu.dcache.writebacks::total 694028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 292192 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 292192 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305480 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3305480 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18304 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18304 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3597672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3597672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3597672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3597672 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411797 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 411797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299249 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299249 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119132 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119132 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8294 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8294 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 693853 # number of writebacks +system.cpu.dcache.writebacks::total 693853 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291952 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291952 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305716 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3305716 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18287 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18287 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3597668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3597668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3597668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3597668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411800 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 411800 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299234 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299234 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119070 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119070 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8297 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 711046 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 711046 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 830178 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 830178 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 711034 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 711034 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 830104 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 830104 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6168747500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6168747500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14918046982 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14918046982 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1646074000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1646074000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126955500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126955500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6169785000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6169785000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14920252482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14920252482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1648301500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1648301500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125755000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125755000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086794482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21086794482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22732868482 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22732868482 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281936500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281936500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281936500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281936500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017171 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017171 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227725 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227725 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21090037482 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21090037482 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22738338982 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22738338982 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281915000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281915000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281915000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281915000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227636 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227636 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017711 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017711 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019014 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14980.069063 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14980.069063 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49851.618492 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49851.618492 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13817.227949 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13817.227949 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15306.908609 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15306.908609 # average LoadLockedReq mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019012 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14982.479359 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14982.479359 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49861.487939 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49861.487939 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13843.130092 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13843.130092 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15156.683138 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15156.683138 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29656.020120 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29656.020120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27383.125645 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27383.125645 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201816.317024 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201816.317024 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.606922 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.606922 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1888653 # number of replacements -system.cpu.icache.tags.tagsinuse 511.315245 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64000443 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1889165 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.877635 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14109307500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.315245 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29661.081583 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29661.081583 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27392.156865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27392.156865 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201815.626305 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201815.626305 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.240722 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.240722 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1888135 # number of replacements +system.cpu.icache.tags.tagsinuse 511.315248 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 63998090 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1888647 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.885681 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14109342500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.315248 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67870984 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67870984 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 64000443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64000443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64000443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64000443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64000443 # number of overall hits -system.cpu.icache.overall_hits::total 64000443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981341 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981341 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981341 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981341 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981341 # number of overall misses -system.cpu.icache.overall_misses::total 1981341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27584584993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27584584993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27584584993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27584584993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27584584993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27584584993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65981784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65981784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65981784 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65981784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65981784 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65981784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.030029 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.030029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.030029 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.030029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.030029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13922.179470 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13922.179470 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13922.179470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13922.179470 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3020 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67867650 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67867650 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 63998090 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 63998090 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 63998090 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 63998090 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 63998090 # number of overall hits +system.cpu.icache.overall_hits::total 63998090 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1980875 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1980875 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1980875 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1980875 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1980875 # number of overall misses +system.cpu.icache.overall_misses::total 1980875 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27580080995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27580080995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27580080995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27580080995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27580080995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27580080995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65978965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65978965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65978965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65978965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65978965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65978965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030023 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.030023 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.030023 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.030023 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.030023 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.030023 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.180915 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13923.180915 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13923.180915 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13923.180915 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2871 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 143 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.827586 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.076923 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1888653 # number of writebacks -system.cpu.icache.writebacks::total 1888653 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92140 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889201 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1889201 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1889201 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1889201 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1889201 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1889201 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1888135 # number of writebacks +system.cpu.icache.writebacks::total 1888135 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92189 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92189 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92189 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92189 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92189 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92189 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888686 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1888686 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1888686 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1888686 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1888686 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1888686 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24719841497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24719841497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24719841497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24719841497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24719841497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24719841497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24710647497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24710647497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24710647497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24710647497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24710647497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24710647497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028632 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028632 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13084.812837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13084.812837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028626 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028626 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028626 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13083.512822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13083.512822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 98099 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65152.234049 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5297886 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163487 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 32.405549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 91189853000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.921050 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.702137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.149180 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 54731.461682 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.835136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 98088 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65152.227961 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5296727 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163476 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 32.400640 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 91191447000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 8.773365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.748453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.912220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54730.793923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158827 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.835126 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994144 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59667 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43918819 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43918819 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52413 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 62451 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 694028 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 694028 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1850699 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1850699 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2792 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2792 # number of UpgradeReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5393 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59670 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43909448 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43909448 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52450 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9977 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 62427 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 693853 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 693853 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1850220 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1850220 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2793 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2793 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 161486 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 161486 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1869293 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1869293 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525699 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 525699 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52413 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10038 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1869293 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687185 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2618929 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52413 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10038 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1869293 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687185 # number of overall hits -system.cpu.l2cache.overall_hits::total 2618929 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 14 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 161466 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 161466 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868784 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1868784 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525651 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 525651 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52450 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 9977 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1868784 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 687117 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2618328 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52450 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 9977 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1868784 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 687117 # number of overall hits +system.cpu.l2cache.overall_hits::total 2618328 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 21 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 135095 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 135095 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19848 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 19848 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13395 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 13395 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 14 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 135099 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 135099 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 19840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13387 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 13387 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 15 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19848 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148490 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 14 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 19840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 148486 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168348 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 15 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19848 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148490 # number of overall misses -system.cpu.l2cache.overall_misses::total 168359 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3912000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 5610000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 148486 # number of overall misses +system.cpu.l2cache.overall_misses::total 168348 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4526000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1704000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 6230000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 143500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 143500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12742200000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12742200000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2140966000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2140966000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1561950000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1561950000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3912000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1698000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2140966000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14304150000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16450726000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3912000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1698000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2140966000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14304150000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16450726000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52427 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10045 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 62472 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 694028 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 694028 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1850699 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1850699 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2797 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2797 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12744525000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12744525000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2137683500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2137683500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1563782000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1563782000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4526000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2137683500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14308307000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16452220500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4526000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2137683500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14308307000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16452220500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52465 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 62449 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 693853 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 693853 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1850220 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1850220 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2798 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2798 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296581 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296581 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1889141 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1889141 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539094 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 539094 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52427 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10045 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1889141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 835675 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2787288 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52427 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10045 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1889141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 835675 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2787288 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000267 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000697 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000336 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001788 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001788 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888624 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1888624 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539038 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 539038 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52465 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 9984 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1888624 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 835603 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2786676 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52465 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 9984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1888624 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 835603 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2786676 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000286 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000701 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001787 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001787 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455508 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.455508 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010506 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010506 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024847 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024847 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000267 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000697 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010506 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.177689 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000267 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000697 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010506 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.177689 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 279428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 242571.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 267142.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455546 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.455546 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010505 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010505 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024835 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024835 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000701 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010505 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.177699 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060412 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000701 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010505 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.177699 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060412 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 301733.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 243428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 283181.818182 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28700 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28700 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94320.293127 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94320.293127 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107868.097541 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107868.097541 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116606.942889 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116606.942889 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97712.186459 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97712.186459 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94334.710101 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94334.710101 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107746.144153 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107746.144153 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116813.475760 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116813.475760 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97727.448500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97727.448500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 90242 # number of writebacks -system.cpu.l2cache.writebacks::total 90242 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 90235 # number of writebacks +system.cpu.l2cache.writebacks::total 90235 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits @@ -1381,29 +1381,29 @@ system.cpu.l2cache.demand_mshr_hits::total 138 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 14 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 15 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 21 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135095 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 135095 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19823 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19823 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13282 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13282 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 14 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135099 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 135099 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19815 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19815 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13274 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13274 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 15 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168221 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 14 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 148373 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 15 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19823 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168221 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19815 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 148373 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168210 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable @@ -1412,145 +1412,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3772000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1628000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 5400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1634000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6010000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 93500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 93500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11391250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11391250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1940936500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1940936500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1418400000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1418400000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3772000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1628000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1940936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12809650000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14755986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3772000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1628000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1940936500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12809650000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14755986500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11393535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11393535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1937570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1937570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1419751500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1419751500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4376000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1937570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12813286500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14756867000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4376000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1937570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12813286500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14756867000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892839000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102035500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892817000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102013500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892839000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102035500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001788 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892817000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102013500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000352 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001787 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455508 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455508 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010493 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024638 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024638 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060353 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060353 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 257142.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010492 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024625 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024625 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060362 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060362 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 273181.818182 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84320.293127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84320.293127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97913.358220 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97913.358220 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106791.145912 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106791.145912 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84334.710101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84334.710101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97783.017916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97783.017916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106957.322586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106957.322586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.995759 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178756.605929 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.288977 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178755.961448 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100370.271329 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.420933 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5483646 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758798 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 178 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100369.896612 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.064485 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5482504 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46081 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557224 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556664 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 784270 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1888653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 148972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 784088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1888135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 149071 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2798 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 539301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 539247 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5673012 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8459795 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241826896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98094045 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40180 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209708 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340170829 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135300 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5917976 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2986955 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025939 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.158953 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5671462 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28809 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128289 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8458023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241760656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98078237 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 39936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340088689 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135331 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5917792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2986371 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026284 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159980 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2909477 97.41% 97.41% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 77478 2.59% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2907876 97.37% 97.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 78495 2.63% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2986955 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5400390498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2986371 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5399114998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 295626 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 298125 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2837677759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2836925219 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1300010143 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1299904639 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18878489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18830489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75816896 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75878391 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30169 # Transaction distribution system.iobus.trans_dist::ReadResp 30169 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1601,25 +1602,25 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43090000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 649000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1627,7 +1628,7 @@ system.iobus.reqLayer16.occupancy 47500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -1635,24 +1636,24 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6166500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6161000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33827500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33823000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187658622 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187589137 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001835 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001834 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 253680812000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001835 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 253684759000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001834 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1660,7 +1661,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1669,14 +1670,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 35726876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 35726876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4357072746 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4357072746 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4392799622 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4392799622 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4392799622 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4392799622 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 35729875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 35729875 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4377211262 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4377211262 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4412941137 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4412941137 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4412941137 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4412941137 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1693,19 +1694,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162394.890909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162394.890909 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120281.381018 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120281.381018 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120535.605916 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120535.605916 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 162408.522727 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162408.522727 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120837.325033 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120837.325033 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121088.276177 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121088.276177 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 222 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -1717,14 +1718,14 @@ system.iocache.demand_mshr_misses::realview.ide 36444 system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 24726876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 24726876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2543825241 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2543825241 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2568552117 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2568552117 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2568552117 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2568552117 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 24729875 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 24729875 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564234451 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2564234451 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2588964326 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2588964326 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2588964326 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2588964326 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1733,90 +1734,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112394.890909 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112394.890909 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70224.857581 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70224.857581 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 339259 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 139343 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112408.522727 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112408.522727 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70788.274376 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70788.274376 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 339223 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 139296 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 511 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34136 # Transaction distribution -system.membus.trans_dist::ReadResp 67481 # Transaction distribution +system.membus.trans_dist::ReadResp 67466 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 126432 # Transaction distribution -system.membus.trans_dist::CleanEvict 8077 # Transaction distribution +system.membus.trans_dist::WritebackDirty 126425 # Transaction distribution +system.membus.trans_dist::CleanEvict 8073 # Transaction distribution system.membus.trans_dist::UpgradeReq 126 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 134974 # Transaction distribution -system.membus.trans_dist::ReadExResp 134974 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33346 # Transaction distribution +system.membus.trans_dist::ReadExReq 134978 # Transaction distribution +system.membus.trans_dist::ReadExResp 134978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33331 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4572 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 449994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557556 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630425 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583932 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16747309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16582780 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746157 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19064429 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) +system.membus.pkt_size::total 19063277 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 5056 # Total snoops (count) system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 266392 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019141 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137021 # Request fanout histogram +system.membus.snoop_fanout::samples 266381 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019149 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137050 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261293 98.09% 98.09% # Request fanout histogram -system.membus.snoop_fanout::1 5099 1.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261280 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 5101 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 266392 # Request fanout histogram -system.membus.reqLayer0.occupancy 84425500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 266381 # Request fanout histogram +system.membus.reqLayer0.occupancy 84417000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1729999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1728499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 876952960 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 876893413 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 984786250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 984678000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1178374 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5966654 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1848,30 +1850,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3b6b744bc..2db3ee4aa 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.554910 # Number of seconds simulated -sim_ticks 47554910274000 # Number of ticks simulated -final_tick 47554910274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.356210 # Number of seconds simulated +sim_ticks 47356210126000 # Number of ticks simulated +final_tick 47356210126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271941 # Simulator instruction rate (inst/s) -host_op_rate 319891 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14743065549 # Simulator tick rate (ticks/s) -host_mem_usage 772792 # Number of bytes of host memory used -host_seconds 3225.58 # Real time elapsed on the host -sim_insts 877166784 # Number of instructions simulated -sim_ops 1031833041 # Number of ops (including micro ops) simulated +host_inst_rate 269105 # Simulator instruction rate (inst/s) +host_op_rate 316551 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14489745940 # Simulator tick rate (ticks/s) +host_mem_usage 771556 # Number of bytes of host memory used +host_seconds 3268.26 # Real time elapsed on the host +sim_insts 879504495 # Number of instructions simulated +sim_ops 1034569807 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 127616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 113728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7300032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13854920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13786176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 105536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 93440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3887680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9545552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11958848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 61215640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7300032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3887680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11187712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74339904 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 139968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 127936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7960960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14481160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15033920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 105216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 97088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3386304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9267600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11152448 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 451392 # Number of bytes read from this memory +system.physmem.bytes_read::total 62203992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7960960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3386304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11347264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74964928 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74360488 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 114063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 216496 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 215409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 60745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 149162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 186857 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 956520 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1161561 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74985512 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2187 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 124390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 226281 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 234905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 144819 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 174257 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7053 # Number of read requests responded to by this memory +system.physmem.num_reads::total 971963 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1171327 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1164135 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 291346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 289900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 200727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 251475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1287262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 235259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1563243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1173901 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 168108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 305792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 317465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 71507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 195700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 235501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1313534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 168108 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 71507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 239615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1583001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1563676 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1563243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 291778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 289900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 200727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 251475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2850939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 956520 # Number of read requests accepted -system.physmem.writeReqs 1164135 # Number of write requests accepted -system.physmem.readBursts 956520 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1164135 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61192448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24832 # Total number of bytes read from write queue -system.physmem.bytesWritten 74357824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61215640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74360488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 388 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1583436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1583001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 168108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 306227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 317465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 71507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 195700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 235501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2896970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 971963 # Number of read requests accepted +system.physmem.writeReqs 1173901 # Number of write requests accepted +system.physmem.readBursts 971963 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1173901 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62180096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 25536 # Total number of bytes read from write queue +system.physmem.bytesWritten 74984000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62203992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74985512 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 399 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50657 # Per bank write bursts -system.physmem.perBankRdBursts::1 60930 # Per bank write bursts -system.physmem.perBankRdBursts::2 49716 # Per bank write bursts -system.physmem.perBankRdBursts::3 55090 # Per bank write bursts -system.physmem.perBankRdBursts::4 56536 # Per bank write bursts -system.physmem.perBankRdBursts::5 68947 # Per bank write bursts -system.physmem.perBankRdBursts::6 58003 # Per bank write bursts -system.physmem.perBankRdBursts::7 60908 # Per bank write bursts -system.physmem.perBankRdBursts::8 53263 # Per bank write bursts -system.physmem.perBankRdBursts::9 106420 # Per bank write bursts -system.physmem.perBankRdBursts::10 50504 # Per bank write bursts -system.physmem.perBankRdBursts::11 59458 # Per bank write bursts -system.physmem.perBankRdBursts::12 56712 # Per bank write bursts -system.physmem.perBankRdBursts::13 60494 # Per bank write bursts -system.physmem.perBankRdBursts::14 55357 # Per bank write bursts -system.physmem.perBankRdBursts::15 53137 # Per bank write bursts -system.physmem.perBankWrBursts::0 68064 # Per bank write bursts -system.physmem.perBankWrBursts::1 74120 # Per bank write bursts -system.physmem.perBankWrBursts::2 68663 # Per bank write bursts -system.physmem.perBankWrBursts::3 72095 # Per bank write bursts -system.physmem.perBankWrBursts::4 73476 # Per bank write bursts -system.physmem.perBankWrBursts::5 80505 # Per bank write bursts -system.physmem.perBankWrBursts::6 71958 # Per bank write bursts -system.physmem.perBankWrBursts::7 74882 # Per bank write bursts -system.physmem.perBankWrBursts::8 69253 # Per bank write bursts -system.physmem.perBankWrBursts::9 72875 # Per bank write bursts -system.physmem.perBankWrBursts::10 68876 # Per bank write bursts -system.physmem.perBankWrBursts::11 75926 # Per bank write bursts -system.physmem.perBankWrBursts::12 72095 # Per bank write bursts -system.physmem.perBankWrBursts::13 75544 # Per bank write bursts -system.physmem.perBankWrBursts::14 71950 # Per bank write bursts -system.physmem.perBankWrBursts::15 71559 # Per bank write bursts +system.physmem.perBankRdBursts::0 55033 # Per bank write bursts +system.physmem.perBankRdBursts::1 62597 # Per bank write bursts +system.physmem.perBankRdBursts::2 50092 # Per bank write bursts +system.physmem.perBankRdBursts::3 57292 # Per bank write bursts +system.physmem.perBankRdBursts::4 55886 # Per bank write bursts +system.physmem.perBankRdBursts::5 65305 # Per bank write bursts +system.physmem.perBankRdBursts::6 62171 # Per bank write bursts +system.physmem.perBankRdBursts::7 60911 # Per bank write bursts +system.physmem.perBankRdBursts::8 55564 # Per bank write bursts +system.physmem.perBankRdBursts::9 110087 # Per bank write bursts +system.physmem.perBankRdBursts::10 50665 # Per bank write bursts +system.physmem.perBankRdBursts::11 58731 # Per bank write bursts +system.physmem.perBankRdBursts::12 55379 # Per bank write bursts +system.physmem.perBankRdBursts::13 59204 # Per bank write bursts +system.physmem.perBankRdBursts::14 58833 # Per bank write bursts +system.physmem.perBankRdBursts::15 53814 # Per bank write bursts +system.physmem.perBankWrBursts::0 70729 # Per bank write bursts +system.physmem.perBankWrBursts::1 73923 # Per bank write bursts +system.physmem.perBankWrBursts::2 67641 # Per bank write bursts +system.physmem.perBankWrBursts::3 73309 # Per bank write bursts +system.physmem.perBankWrBursts::4 73460 # Per bank write bursts +system.physmem.perBankWrBursts::5 77994 # Per bank write bursts +system.physmem.perBankWrBursts::6 75119 # Per bank write bursts +system.physmem.perBankWrBursts::7 77047 # Per bank write bursts +system.physmem.perBankWrBursts::8 72172 # Per bank write bursts +system.physmem.perBankWrBursts::9 76177 # Per bank write bursts +system.physmem.perBankWrBursts::10 69310 # Per bank write bursts +system.physmem.perBankWrBursts::11 74055 # Per bank write bursts +system.physmem.perBankWrBursts::12 71196 # Per bank write bursts +system.physmem.perBankWrBursts::13 73730 # Per bank write bursts +system.physmem.perBankWrBursts::14 72781 # Per bank write bursts +system.physmem.perBankWrBursts::15 72982 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 408 # Number of times write queue was full causing retry -system.physmem.totGap 47554908178500 # Total gap between requests +system.physmem.numWrRetry 338 # Number of times write queue was full causing retry +system.physmem.totGap 47356208030500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 956490 # Read request sizes (log2) +system.physmem.readPktSize::6 971933 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1161561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 589555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 157739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 20914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1171327 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 599542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 159109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 23819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,188 +189,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 933 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 917155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 147.793592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.753334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 195.501852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 602356 65.68% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188931 20.60% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45653 4.98% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20839 2.27% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15350 1.67% 95.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9574 1.04% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6849 0.75% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5486 0.60% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22117 2.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 917155 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56545 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.908586 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 165.794592 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 56543 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 24305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 73010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 67464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 769 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 927860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 147.827612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.770435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 195.442358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 609464 65.68% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 190800 20.56% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46263 4.99% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21195 2.28% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15500 1.67% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9774 1.05% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7067 0.76% 97.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5586 0.60% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22211 2.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 927860 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.014939 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.898277 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57097 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56545 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56545 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.547193 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.712168 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.106429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48673 86.08% 86.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2227 3.94% 90.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 713 1.26% 91.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 569 1.01% 92.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 930 1.64% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 406 0.72% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 286 0.51% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 280 0.50% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 183 0.32% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 127 0.22% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 115 0.20% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 143 0.25% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 579 1.02% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 140 0.25% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 130 0.23% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 128 0.23% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 106 0.19% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 75 0.13% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 85 0.15% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 94 0.17% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 75 0.13% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 62 0.11% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 61 0.11% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 71 0.13% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 39 0.07% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 37 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 45 0.08% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 34 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 51 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 18 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 57099 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57099 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.519186 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.696547 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.054604 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49168 86.11% 86.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2307 4.04% 90.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 623 1.09% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 607 1.06% 92.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 970 1.70% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 377 0.66% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 342 0.60% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 248 0.43% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 171 0.30% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 147 0.26% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 125 0.22% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 141 0.25% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 491 0.86% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 181 0.32% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 140 0.25% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 149 0.26% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 103 0.18% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 79 0.14% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 87 0.15% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 90 0.16% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 76 0.13% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 61 0.11% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 62 0.11% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 70 0.12% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 41 0.07% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 40 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 42 0.07% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 34 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 42 0.07% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 20 0.04% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 17 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56545 # Writes before turning the bus around for reads -system.physmem.totQLat 49127716705 # Total ticks spent queuing -system.physmem.totMemAccLat 67055191705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4780660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51381.73 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57099 # Writes before turning the bus around for reads +system.physmem.totQLat 49354955217 # Total ticks spent queuing +system.physmem.totMemAccLat 67571780217 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4857820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 50799.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70131.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 69549.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 713884 # Number of row buffer hits during reads -system.physmem.writeRowHits 486930 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.91 # Row buffer hit rate for writes -system.physmem.avgGap 22424632.10 # Average gap between requests -system.physmem.pageHitRate 56.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3312517320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1760633325 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3290019180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3047242860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 39654114240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43514746200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2086179840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 77547983010 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 55697482080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11319929946090 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11549857795695 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.874137 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47454012976233 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3696049077 # Time in different power states -system.physmem_0.memoryStateTime::REF 16847240000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47138905885000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 145045339612 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80353958440 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 170061801871 # Time in different power states -system.physmem_1.actEnergy 3235997940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1719969900 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3536763300 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3017567160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 38496747120.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 44079949650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2012350560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 72751641060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 54144086400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11323086477345 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11546099446905 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.795105 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47452962329328 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3512995347 # Time in different power states -system.physmem_1.memoryStateTime::REF 16356664000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47152420144750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 141000345458 # Time in different power states -system.physmem_1.memoryStateTime::ACT 82076677575 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 159543446870 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.53 # Average write queue length when enqueuing +system.physmem.readRowHits 725116 # Number of row buffer hits during reads +system.physmem.writeRowHits 490210 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.84 # Row buffer hit rate for writes +system.physmem.avgGap 22068597.09 # Average gap between requests +system.physmem.pageHitRate 56.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3347988840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1779490680 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3350709180 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3075738840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 40224500160.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43885079760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2109996960 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 79595636190 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 56472597600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11270458828185 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11504320668105 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.931616 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47254429054365 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3740889550 # Time in different power states +system.physmem_0.memoryStateTime::REF 17088544000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46932815651000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 147063936092 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80948731835 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 174552373523 # Time in different power states +system.physmem_1.actEnergy 3276952980 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1741738020 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3586257780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3040143660 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 38004420480.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 43585213590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1995622560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 72860280210 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 53203975680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11275978868760 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11497290812280 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.783170 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47255392508641 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3486165610 # Time in different power states +system.physmem_1.memoryStateTime::REF 16146094000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46957059679500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 138551420004 # Time in different power states +system.physmem_1.memoryStateTime::ACT 81185307499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 159781459387 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -386,41 +385,41 @@ system.realview.nvmem.num_reads::cpu1.data 1 # system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 137627857 # Number of BP lookups -system.cpu0.branchPred.condPredicted 96352530 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6353129 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 102612546 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71378761 # Number of BTB hits +system.cpu0.branchPred.lookups 135721275 # Number of BP lookups +system.cpu0.branchPred.condPredicted 95221356 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6297780 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 101561419 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 70514394 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.561436 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16463463 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1088270 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3669510 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2436336 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1233174 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 447439 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 69.430296 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16061922 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1062204 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3676908 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2416966 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1259942 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 447333 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,66 +449,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 282889 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 282889 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9418 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82700 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 282889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 282889 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 282889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 92118 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 90947 98.73% 98.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 867 0.94% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 159 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 92118 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 280305 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 280305 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9673 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80745 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 280305 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 280305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 280305 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 90418 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 89075 98.51% 98.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1011 1.12% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 175 0.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 41 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 21 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 90418 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 82700 89.78% 89.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9418 10.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92118 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 282889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 80745 89.30% 89.30% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9673 10.70% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 90418 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 280305 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 282889 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92118 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 280305 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90418 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92118 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 375007 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90418 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 370723 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 87675894 # DTB read hits -system.cpu0.dtb.read_misses 234519 # DTB read misses -system.cpu0.dtb.write_hits 78239753 # DTB write hits -system.cpu0.dtb.write_misses 48370 # DTB write misses +system.cpu0.dtb.read_hits 85620412 # DTB read hits +system.cpu0.dtb.read_misses 232360 # DTB read misses +system.cpu0.dtb.write_hits 76323418 # DTB write hits +system.cpu0.dtb.write_misses 47945 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38151 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9397 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 37568 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2099 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10030 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11689 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 87910413 # DTB read accesses -system.cpu0.dtb.write_accesses 78288123 # DTB write accesses +system.cpu0.dtb.perms_faults 11718 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85852772 # DTB read accesses +system.cpu0.dtb.write_accesses 76371363 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165915647 # DTB hits -system.cpu0.dtb.misses 282889 # DTB misses -system.cpu0.dtb.accesses 166198536 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 161943830 # DTB hits +system.cpu0.dtb.misses 280305 # DTB misses +system.cpu0.dtb.accesses 162224135 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -539,903 +536,906 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 69273 # Table walker walks requested -system.cpu0.itb.walker.walksLong 69273 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 583 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61330 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 69273 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 69273 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 69273 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 61913 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26255.972090 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 60695 98.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 852 1.38% 99.41% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 248 0.40% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 49 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 39 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 61913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 68220 # Table walker walks requested +system.cpu0.itb.walker.walksLong 68220 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 613 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59689 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 68220 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 68220 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 68220 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60302 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26595.826009 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 58891 97.66% 97.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1009 1.67% 99.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 274 0.45% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.12% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60302 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61330 99.06% 99.06% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 583 0.94% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61913 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 59689 98.98% 98.98% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 613 1.02% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60302 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69273 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69273 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68220 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68220 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 131186 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 244690597 # ITB inst hits -system.cpu0.itb.inst_misses 69273 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60302 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60302 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 128522 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 240780512 # ITB inst hits +system.cpu0.itb.inst_misses 68220 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27059 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 26473 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 167788 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 160298 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 244759870 # ITB inst accesses -system.cpu0.itb.hits 244690597 # DTB hits -system.cpu0.itb.misses 69273 # DTB misses -system.cpu0.itb.accesses 244759870 # DTB accesses -system.cpu0.numPwrStateTransitions 27904 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13952 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3372797482.084218 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 110921496988.059006 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3863 27.69% 27.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10067 72.15% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.92% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 8 0.06% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 240848732 # ITB inst accesses +system.cpu0.itb.hits 240780512 # DTB hits +system.cpu0.itb.misses 68220 # DTB misses +system.cpu0.itb.accesses 240848732 # DTB accesses +system.cpu0.numPwrStateTransitions 27604 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13802 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3395512179.708375 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 87569621243.897629 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3847 27.87% 27.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9929 71.94% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7351146409252 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13952 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 497639803961 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 995321471 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470353787292 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13802 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 491351021665 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 982743358 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 452001209 # Number of instructions committed -system.cpu0.committedOps 531851100 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 46239027 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5092 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 94115325169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.202033 # CPI: cycles per instruction -system.cpu0.ipc 0.454126 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 368287155 69.25% 69.25% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1118982 0.21% 69.46% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 57276 0.01% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 8 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 13 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 21 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 85306 0.02% 69.48% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::MemRead 84333617 15.86% 85.34% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 77481840 14.57% 99.91% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 68467 0.01% 99.92% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 418414 0.08% 100.00% # Class of committed instruction +system.cpu0.committedInsts 443442317 # Number of instructions committed +system.cpu0.committedOps 521139520 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 46171758 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4942 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93730487058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.216170 # CPI: cycles per instruction +system.cpu0.ipc 0.451229 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 361587453 69.38% 69.38% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1073144 0.21% 69.59% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 57197 0.01% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 8 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 13 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 21 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 48874 0.01% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::MemRead 82336787 15.80% 85.41% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 75604792 14.51% 99.92% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 54276 0.01% 99.93% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 376955 0.07% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 531851100 # Class of committed instruction +system.cpu0.op_class_0::total 521139520 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13952 # number of quiesce instructions executed -system.cpu0.tickCycles 729574114 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 265747357 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5787900 # number of replacements -system.cpu0.dcache.tags.tagsinuse 490.209920 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157471988 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5788412 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.204696 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13802 # number of quiesce instructions executed +system.cpu0.tickCycles 716804238 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 265939120 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5714630 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.374360 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 153605175 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5715141 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.876883 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.209920 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.957441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 334937152 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 334937152 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80549957 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80549957 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72496805 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72496805 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 269794 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 269794 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177007 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 177007 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1734640 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1734640 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1715473 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1715473 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153223769 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153223769 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153493563 # number of overall hits -system.cpu0.dcache.overall_hits::total 153493563 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3263198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3263198 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2445366 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2445366 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673099 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 673099 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844507 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 844507 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 169054 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 169054 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187078 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 187078 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6553071 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6553071 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7226170 # number of overall misses -system.cpu0.dcache.overall_misses::total 7226170 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52395902500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52395902500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52490790500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52490790500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27335813500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 27335813500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2555333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2555333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4463485500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4463485500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2023000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2023000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 132222506500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 132222506500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83813155 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83813155 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74942171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74942171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 942893 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 942893 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1021514 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1021514 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1903694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1903694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1902551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1902551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159776840 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159776840 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 160719733 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 160719733 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038934 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038934 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032630 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032630 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713866 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713866 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.826721 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.826721 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088803 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088803 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098330 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098330 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041014 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041014 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044961 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044961 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.374360 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983153 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983153 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 326958988 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 326958988 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78624149 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78624149 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70655306 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 70655306 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268473 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 268473 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172491 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 172491 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1691736 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1691736 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1666426 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1666426 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 149451946 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149451946 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149720419 # number of overall hits +system.cpu0.dcache.overall_hits::total 149720419 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3212821 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3212821 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2434459 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2434459 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667240 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 667240 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831306 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 831306 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163515 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 163515 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187633 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 187633 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6478586 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6478586 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7145826 # number of overall misses +system.cpu0.dcache.overall_misses::total 7145826 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52300502500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 52300502500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52442906000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 52442906000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26430842500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 26430842500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2572412500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2572412500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4480220000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4480220000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2147000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2147000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 131174251000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 131174251000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 81836970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 81836970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73089765 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73089765 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935713 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 935713 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1003797 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1003797 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1855251 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1855251 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1854059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1854059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 155930532 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 155930532 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156866245 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156866245 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039259 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039259 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033308 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713082 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713082 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.828161 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.828161 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088136 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088136 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101201 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101201 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045554 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045554 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20177.182042 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18297.729849 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20247.358143 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18356.765334 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5787917 # number of writebacks -system.cpu0.dcache.writebacks::total 5787917 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 205447 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 205447 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1015907 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1015907 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 99 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 37 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 37 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1221453 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1221453 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1221453 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1221453 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3057751 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3057751 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1429459 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1429459 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 670780 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 670780 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 844408 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 844408 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123170 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123170 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187041 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 187041 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5331618 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5331618 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6002398 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6002398 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31212 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61967 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44254087500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44254087500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29600010500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29600010500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15858321000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15858321000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26484603000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26484603000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1676878500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1676878500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4275603000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4275603000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1773000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1773000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 100338701000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 116197022000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6038825000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6038825000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6038825000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6038825000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019074 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019074 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711406 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711406 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.826624 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.826624 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098311 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098311 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033369 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037347 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037347 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5714633 # number of writebacks +system.cpu0.dcache.writebacks::total 5714633 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202792 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202792 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1014502 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1014502 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 93 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 93 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43372 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43372 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 49 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 49 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1217387 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1217387 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1217387 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1217387 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3010029 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3010029 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419957 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1419957 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664995 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 664995 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 831213 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 831213 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120143 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120143 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187584 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 187584 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5261199 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5261199 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5926194 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5926194 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31550 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62751 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44196910500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44196910500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29509664500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29509664500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16065417000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16065417000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25593186000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25593186000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1671520500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1671520500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4291457000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4291457000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1958500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1958500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99299761000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 99299761000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 115365178000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6087891000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6087891000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6087891000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6087891000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036781 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036781 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019428 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019428 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710683 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710683 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.828069 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.828069 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064758 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064758 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101175 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101175 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033741 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033741 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037779 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037779 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9773833 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.928996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 234741496 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9774345 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.016085 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22886662000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928996 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 9611464 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.928699 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 231001616 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9611976 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.032688 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22883257000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928699 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 426 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 498806059 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 498806059 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 234741496 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 234741496 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 234741496 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 234741496 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 234741496 # number of overall hits -system.cpu0.icache.overall_hits::total 234741496 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9774356 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9774356 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9774356 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9774356 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9774356 # number of overall misses -system.cpu0.icache.overall_misses::total 9774356 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99441985000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 99441985000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 99441985000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 99441985000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 99441985000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 99441985000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 244515852 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 244515852 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 244515852 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 244515852 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 244515852 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 244515852 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039974 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039974 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039974 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039974 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039974 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039974 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10173.763366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10173.763366 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 490839190 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 490839190 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 231001616 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 231001616 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 231001616 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 231001616 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 231001616 # number of overall hits +system.cpu0.icache.overall_hits::total 231001616 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9611986 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9611986 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9611986 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9611986 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9611986 # number of overall misses +system.cpu0.icache.overall_misses::total 9611986 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98657772000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 98657772000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 98657772000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 98657772000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 98657772000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 98657772000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 240613602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 240613602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 240613602 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 240613602 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 240613602 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 240613602 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039948 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039948 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039948 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039948 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039948 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039948 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10264.036173 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10264.036173 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 9773833 # number of writebacks -system.cpu0.icache.writebacks::total 9773833 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9774356 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9774356 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9774356 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9774356 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9774356 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9774356 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 9611464 # number of writebacks +system.cpu0.icache.writebacks::total 9611464 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9611986 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9611986 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9611986 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9611986 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9611986 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9611986 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94554807500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 94554807500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94554807500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 94554807500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94554807500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 94554807500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93851779000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 93851779000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93851779000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 93851779000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93851779000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 93851779000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039974 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039974 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039974 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9673.763417 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039948 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039948 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9764.036173 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7608993 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7610336 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1188 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7434042 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7435434 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1234 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1005416 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2646552 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15691.473570 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 14028250 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2662377 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.269070 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 974582 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2611270 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15687.218696 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 13797239 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2627042 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.252005 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15348.189818 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.039011 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 8.868609 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 302.376132 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.936779 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000541 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018456 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.957732 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 352 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15319.283860 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.805682 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.313962 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 298.815192 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.935015 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002613 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001606 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018238 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.957472 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 263 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 65 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1727 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6563 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2911 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021484 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 89 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2136 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5462 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5455 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2257 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016052 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 534452534 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 534452534 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527649 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180298 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 707947 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3832122 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3832122 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11726658 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11726658 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 904488 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 904488 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9076171 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 9076171 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2875219 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2875219 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 241369 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 241369 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527649 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180298 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 9076171 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3779707 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13563825 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527649 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180298 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9076171 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3779707 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13563825 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21665 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 31785 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246294 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 246294 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187036 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 187036 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 286789 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 286789 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 698184 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 698184 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 976175 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 976175 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601118 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 601118 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21665 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 698184 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1262964 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1992933 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21665 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 698184 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1262964 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1992933 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 696360500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 404225000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1100585500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 910928500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 910928500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 289294500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 289294500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1705497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1705497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15428607998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 15428607998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25059292500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25059292500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37051733995 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 37051733995 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 336301500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 336301500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 696360500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 404225000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25059292500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 52480341993 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 78640219993 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 696360500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 404225000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25059292500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 52480341993 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 78640219993 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 549314 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 190418 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 739732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3832122 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3832122 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 11726658 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 11726658 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 246295 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 246295 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187036 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 187036 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1191277 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1191277 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9774355 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 9774355 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3851394 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3851394 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 842487 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 842487 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 549314 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 190418 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9774355 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5042671 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 15556758 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 549314 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 190418 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9774355 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5042671 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 15556758 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053146 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.042968 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999996 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999996 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.tag_accesses 526460646 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 526460646 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522971 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 177971 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 700942 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3820006 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3820006 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 11503050 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 11503050 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 900259 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 900259 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8923530 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 8923530 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2824509 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2824509 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229490 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 229490 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522971 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 177971 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 8923530 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3724768 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 13349240 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522971 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 177971 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 8923530 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3724768 # number of overall hits +system.cpu0.l2cache.overall_hits::total 13349240 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20616 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9971 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 30587 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242554 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 242554 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187582 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 187582 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 283527 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 283527 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688455 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 688455 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 970291 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 970291 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601723 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 601723 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20616 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9971 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 688455 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1253818 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1972860 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20616 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9971 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 688455 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1253818 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1972860 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 693953500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 416737500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1110691000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 877430000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 877430000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 285529500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 285529500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1883000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1883000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15417318498 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 15417318498 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25525674000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25525674000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37603567991 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 37603567991 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 693953500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 416737500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25525674000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 53020886489 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 79657251489 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 693953500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 416737500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25525674000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 53020886489 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 79657251489 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 543587 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 187942 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 731529 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3820006 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3820006 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 11503050 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 11503050 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242554 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 242554 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187582 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 187582 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183786 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1183786 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9611985 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 9611985 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3794800 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3794800 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831213 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 831213 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 543587 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 187942 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 9611985 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4978586 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 15322100 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 543587 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 187942 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 9611985 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4978586 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 15322100 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053054 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.041812 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240741 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240741 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071430 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071430 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.253460 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.253460 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.713504 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.713504 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053146 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071430 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250455 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.128107 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053146 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071430 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250455 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.128107 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39943.181818 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34625.939909 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3698.541174 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3698.541174 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1546.731645 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1546.731645 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 341099.400000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 341099.400000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53797.767690 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53797.767690 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35892.103657 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35892.103657 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37956.036566 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37956.036566 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 559.460039 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 559.460039 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39459.540282 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39459.540282 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.239509 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.239509 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071625 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071625 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255690 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255690 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.723910 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.723910 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053054 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071625 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251842 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.128759 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053054 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071625 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251842 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.128759 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41794.955371 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36312.518390 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3617.462503 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3617.462503 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1522.158309 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1522.158309 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54376.897079 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54376.897079 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37076.750114 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37076.750114 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38754.938458 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38754.938458 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.172837 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.172837 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40376.535329 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40376.535329 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 45829 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1629804 # number of writebacks -system.cpu0.l2cache.writebacks::total 1629804 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 24 # number of ReadReq MSHR hits +system.cpu0.l2cache.unused_prefetches 44451 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1620068 # number of writebacks +system.cpu0.l2cache.writebacks::total 1620068 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 98 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8277 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 8277 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 866 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 866 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 24 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8857 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 8857 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 996 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 996 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 98 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9143 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 9277 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 24 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9853 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 9980 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 98 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9143 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 9277 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21641 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10022 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 31663 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782860 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 782860 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246294 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 246294 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187036 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187036 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 278512 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 278512 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 698172 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 698172 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 975309 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 975309 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601115 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 601115 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21641 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10022 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 698172 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253821 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21641 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10022 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 698172 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253821 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782860 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2766516 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9853 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 9980 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20593 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9873 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 30466 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 782341 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242554 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 242554 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187582 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187582 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274670 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 274670 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688449 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688449 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 969295 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 969295 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601721 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 601721 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20593 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9873 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688449 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243965 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1962880 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20593 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9873 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688449 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243965 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2745221 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83496 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83834 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114251 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 342540500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 908484500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36299233693 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4539562995 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4539562995 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2868254998 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2868254998 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1441497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1441497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12630779498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12630779498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20869901000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20869901000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31074032995 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31074032995 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19885865000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19885865000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 342540500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20869901000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43704812493 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 65483197993 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 342540500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20869901000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43704812493 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115035 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 355875500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 925633500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38599728272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4476827494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4476827494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2879854497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2879854497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1583000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1583000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12562742498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12562742498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21394767500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21394767500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31646923991 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31646923991 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19132934000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19132934000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 355875500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21394767500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44209666489 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 66530067489 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 355875500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21394767500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44209666489 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 105129795761 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788958500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10532292500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5835246500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10578580500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788958500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10532292500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042803 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5835246500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10578580500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041647 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999996 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999996 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233793 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233793 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071429 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.253235 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253235 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.713501 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.713501 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127511 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.232027 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.232027 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071624 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255427 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255427 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.723907 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.723907 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128108 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177834 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.179167 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 791500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 791500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 31945858 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16286466 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2971 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 662323 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 662303 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 20 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 897088 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14618500 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30756 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 30755 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5466694 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11729628 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1381452 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1000780 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 31463839 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16044170 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3048 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 652134 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 652077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 57 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 887708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14387458 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5457517 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11506087 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1359708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 999352 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 445154 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338634 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 499902 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1222912 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1199223 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9774356 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4899750 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 895142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 842487 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29427111 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18719100 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 397503 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1155819 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 49699533 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1254430144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699985190 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1523344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4394512 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1960333190 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5744069 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 111836388 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 22520641 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.042476 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.201677 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 454749 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343952 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 493156 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1220335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1191280 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9611986 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4900402 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 909564 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 832554 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28940003 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18484921 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391848 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1143553 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 48960325 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1233646912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690994144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1503536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4348696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1930493288 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5822948 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 111810824 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 22356517 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.042093 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.200815 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21564077 95.75% 95.75% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 956544 4.25% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 20 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21415512 95.79% 95.79% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 940948 4.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 57 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22520641 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 31868357980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22356517 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 31390166976 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 188944290 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 183129639 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14742648604 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14498904485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8252120363 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8149348322 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 207185798 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 204016279 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 606624760 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 600088255 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 130393488 # Number of BP lookups -system.cpu1.branchPred.condPredicted 92735412 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5902942 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 97710710 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 68499677 # Number of BTB hits +system.cpu1.branchPred.lookups 132997996 # Number of BP lookups +system.cpu1.branchPred.condPredicted 94215152 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6033479 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 99520242 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 69476937 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 70.104574 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15029088 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 982146 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3431599 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2322480 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1109119 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 398100 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 69.811865 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15575496 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1022946 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3462102 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2360825 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1101277 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 401735 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1465,64 +1465,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 266586 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9178 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75276 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84454 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 83574 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 653 0.77% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 133 0.16% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 271949 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 271949 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9428 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76874 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 271949 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 271949 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 271949 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 86302 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 85344 98.89% 98.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 718 0.83% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 138 0.16% 99.88% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 30 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84454 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 112342944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 112342944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 112342944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 75276 89.13% 89.13% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9178 10.87% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84454 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 32 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 86302 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 114608944 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 114608944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 114608944 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 76874 89.08% 89.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9428 10.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 86302 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271949 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84454 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271949 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86302 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84454 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 351040 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86302 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 358251 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83602508 # DTB read hits -system.cpu1.dtb.read_misses 221634 # DTB read misses -system.cpu1.dtb.write_hits 72407946 # DTB write hits -system.cpu1.dtb.write_misses 44952 # DTB write misses +system.cpu1.dtb.read_hits 86154833 # DTB read hits +system.cpu1.dtb.read_misses 225974 # DTB read misses +system.cpu1.dtb.write_hits 74805729 # DTB write hits +system.cpu1.dtb.write_misses 45975 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35586 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1113 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7045 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 36571 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1221 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7188 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10293 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83824142 # DTB read accesses -system.cpu1.dtb.write_accesses 72452898 # DTB write accesses +system.cpu1.dtb.perms_faults 10263 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 86380807 # DTB read accesses +system.cpu1.dtb.write_accesses 74851704 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 156010454 # DTB hits -system.cpu1.dtb.misses 266586 # DTB misses -system.cpu1.dtb.accesses 156277040 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 160960562 # DTB hits +system.cpu1.dtb.misses 271949 # DTB misses +system.cpu1.dtb.accesses 161232511 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1552,897 +1551,908 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60007 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60007 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 568 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49765 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60007 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60007 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60007 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 50333 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25530.089603 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 49435 98.22% 98.22% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 638 1.27% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 189 0.38% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 38 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60899 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60899 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 513 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50941 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60899 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60899 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60899 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51454 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25618.018036 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 50489 98.12% 98.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 670 1.30% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.41% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 46 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 14 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 50333 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 111619444 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 111619444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 111619444 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 49765 98.87% 98.87% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 568 1.13% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 50333 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 13 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 51454 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 113972444 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 113972444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 113972444 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50941 99.00% 99.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 513 1.00% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51454 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60007 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60007 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60899 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60899 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 50333 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 50333 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 110340 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 231314016 # ITB inst hits -system.cpu1.itb.inst_misses 60007 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 112353 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 236231380 # ITB inst hits +system.cpu1.itb.inst_misses 60899 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25531 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 26538 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 167507 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 178013 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 231374023 # ITB inst accesses -system.cpu1.itb.hits 231314016 # DTB hits -system.cpu1.itb.misses 60007 # DTB misses -system.cpu1.itb.accesses 231374023 # DTB accesses -system.cpu1.numPwrStateTransitions 9626 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4813 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9788374174.243299 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 115006828751.685410 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3303 68.63% 68.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1483 30.81% 99.44% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.48% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 18 0.37% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 236292279 # ITB inst accesses +system.cpu1.itb.hits 236231380 # DTB hits +system.cpu1.itb.misses 60899 # DTB misses +system.cpu1.itb.accesses 236292279 # DTB accesses +system.cpu1.numPwrStateTransitions 9440 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4720 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9937322156.794067 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 214697400239.899719 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3380 71.61% 71.61% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1320 27.97% 99.58% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.11% 99.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1988779353616 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4813 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 443465373367 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 886937326 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813594348000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4720 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 452049545932 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 904105497 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 425165575 # Number of instructions committed -system.cpu1.committedOps 499981941 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 45360018 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94223530921 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.086099 # CPI: cycles per instruction -system.cpu1.ipc 0.479364 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 346104827 69.22% 69.22% # Class of committed instruction -system.cpu1.op_class_0::IntMult 1095440 0.22% 69.44% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 59698 0.01% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 26657 0.01% 69.46% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::MemRead 80537576 16.11% 85.57% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 71850356 14.37% 99.94% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 41546 0.01% 99.95% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 265841 0.05% 100.00% # Class of committed instruction +system.cpu1.committedInsts 436062178 # Number of instructions committed +system.cpu1.committedOps 513430287 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 45590191 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93808990671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.073341 # CPI: cycles per instruction +system.cpu1.ipc 0.482313 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 354600208 69.06% 69.06% # Class of committed instruction +system.cpu1.op_class_0::IntMult 1143323 0.22% 69.29% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 59569 0.01% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 63096 0.01% 69.31% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.op_class_0::MemRead 82989666 16.16% 85.48% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 74191847 14.45% 99.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 64253 0.01% 99.94% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 318324 0.06% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 499981941 # Class of committed instruction +system.cpu1.op_class_0::total 513430287 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4813 # number of quiesce instructions executed -system.cpu1.tickCycles 688160387 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 198776939 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4915770 # number of replacements -system.cpu1.dcache.tags.tagsinuse 461.565771 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 148821179 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4916282 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.271083 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378532705500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 461.565771 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.901496 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.901496 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 4720 # number of quiesce instructions executed +system.cpu1.tickCycles 704305988 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 199799509 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5048947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.228585 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153590869 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5049459 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.417292 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378525599500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.228585 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.812946 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.812946 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 314637839 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 314637839 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 76998524 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76998524 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 67544283 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 67544283 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 228025 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 228025 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 143759 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 143759 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733263 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1733263 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1698082 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1698082 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 144686566 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 144686566 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 144914591 # number of overall hits -system.cpu1.dcache.overall_hits::total 144914591 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2997503 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2997503 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2132920 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2132920 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 598160 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 598160 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 396373 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 396373 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156072 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190006 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 190006 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5526796 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5526796 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6124956 # number of overall misses -system.cpu1.dcache.overall_misses::total 6124956 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46710580500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 46710580500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40169374000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40169374000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10226397500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10226397500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2373794500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2373794500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4526922000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4526922000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1761500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1761500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 97106352000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 97106352000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 97106352000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 97106352000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79996027 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79996027 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69677203 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69677203 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 826185 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 826185 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 540132 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 540132 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1889335 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1889335 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1888088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1888088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 150213362 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 150213362 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 151039547 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 151039547 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037471 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037471 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030611 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030611 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.724002 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.724002 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733845 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733845 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100634 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100634 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036793 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036793 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040552 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040552 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 324622701 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 324622701 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 79356977 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79356977 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69837106 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69837106 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 233112 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 233112 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 147127 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 147127 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782955 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1782955 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1749534 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1749534 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 149341210 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 149341210 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 149574322 # number of overall hits +system.cpu1.dcache.overall_hits::total 149574322 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3104936 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3104936 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2154320 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2154320 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 600203 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 600203 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 416637 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 416637 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162547 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 162547 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194652 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 194652 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5675893 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5675893 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6276096 # number of overall misses +system.cpu1.dcache.overall_misses::total 6276096 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47629871000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 47629871000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40774475000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 40774475000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9727566000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 9727566000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2415502000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2415502000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4643846000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4643846000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2158500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2158500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 98131912000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 98131912000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 98131912000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 98131912000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82461913 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82461913 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71991426 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71991426 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833315 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 833315 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 563764 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 563764 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1945502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944186 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1944186 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 155017103 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 155017103 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155850418 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155850418 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037653 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037653 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029925 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029925 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.720259 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.720259 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739027 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739027 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083550 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083550 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100120 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100120 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036615 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036615 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040270 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040270 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17570.098842 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15854.212177 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17289.246291 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15635.820740 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4915771 # number of writebacks -system.cpu1.dcache.writebacks::total 4915771 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147995 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 147995 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 874601 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 874601 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 38344 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 38344 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 50 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1022654 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1022654 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1022654 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1022654 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2849508 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2849508 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1258319 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1258319 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 597912 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 597912 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 396315 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 396315 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117728 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117728 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189956 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 189956 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4504142 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4504142 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5102054 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5102054 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7183 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14692 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40476665500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40476665500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23125073000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23125073000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13939684500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13939684500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9826633500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9826633500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1586206000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1586206000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4335749000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4335749000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1584500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1584500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73428372000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 73428372000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87368056500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87368056500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 918087500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 918087500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 918087500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 918087500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035621 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035621 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018059 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018059 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.723702 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.723702 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.733737 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.733737 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062312 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062312 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100608 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100608 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029985 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029985 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033780 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033780 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5048949 # number of writebacks +system.cpu1.dcache.writebacks::total 5048949 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 157294 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 157294 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 878635 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 878635 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 59 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 59 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39126 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39126 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 65 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1035988 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1035988 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1035988 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1035988 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2947642 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2947642 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1275685 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1275685 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599894 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 599894 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 416578 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 416578 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123421 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123421 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194587 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 194587 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4639905 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4639905 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5239799 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5239799 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6968 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14155 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41244047000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41244047000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23526690000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23526690000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13870615000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13870615000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9306680500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9306680500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1636714500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1636714500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4447799000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4447799000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1876000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1876000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74077417500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 74077417500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87948032500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 87948032500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 882714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 882714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 882714500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 882714500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035745 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035745 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017720 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.719889 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.719889 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738923 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738923 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063439 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063439 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100087 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100087 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033621 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033621 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 8832346 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.234959 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 222308626 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8832858 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.168369 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8368864848000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.234959 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990693 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990693 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 9106015 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.214941 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 226941610 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9106527 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.920764 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8368863514500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.214941 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990654 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990654 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 471115826 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 471115826 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 222308626 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 222308626 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 222308626 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 222308626 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 222308626 # number of overall hits -system.cpu1.icache.overall_hits::total 222308626 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8832858 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8832858 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8832858 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8832858 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8832858 # number of overall misses -system.cpu1.icache.overall_misses::total 8832858 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91672034000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 91672034000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 91672034000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 91672034000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 91672034000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 91672034000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 231141484 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 231141484 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 231141484 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 231141484 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 231141484 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 231141484 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038214 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038214 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038214 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038214 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038214 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038214 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10378.524595 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10378.524595 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 481202803 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 481202803 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 226941610 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 226941610 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 226941610 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 226941610 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 226941610 # number of overall hits +system.cpu1.icache.overall_hits::total 226941610 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9106528 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9106528 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9106528 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9106528 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9106528 # number of overall misses +system.cpu1.icache.overall_misses::total 9106528 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93334039500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 93334039500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 93334039500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 93334039500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 93334039500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 93334039500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 236048138 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 236048138 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 236048138 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 236048138 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 236048138 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 236048138 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038579 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038579 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038579 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038579 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038579 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038579 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10249.135510 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10249.135510 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 8832346 # number of writebacks -system.cpu1.icache.writebacks::total 8832346 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8832858 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8832858 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8832858 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8832858 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8832858 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8832858 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 9106015 # number of writebacks +system.cpu1.icache.writebacks::total 9106015 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9106528 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9106528 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9106528 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9106528 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9106528 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9106528 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 87255605000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 87255605000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 87255605000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 87255605000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 87255605000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 87255605000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9824500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9824500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9824500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9824500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038214 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038214 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038214 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9878.524595 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6928823 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6928917 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 84 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88780776000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 88780776000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88780776000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 88780776000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88780776000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 88780776000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9602500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9602500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9602500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9602500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038579 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9749.135565 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104941 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7105044 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 861587 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2157597 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13047.513497 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 12560684 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2173028 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.780268 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 891372 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2193537 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13101.642441 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 12964075 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2209317 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.867911 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 48.343114 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 32.192156 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.258823 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.776472 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002951 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001965 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014969 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.796357 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 270 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15088 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 29.247108 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.647207 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 236.020843 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.782454 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001785 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001016 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014406 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.799661 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 358 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15375 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 74 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 832 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6150 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6722 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016479 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.920898 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 472979438 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 472979438 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 496781 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150336 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 647117 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3051311 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3051311 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 10695223 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 10695223 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 813214 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 813214 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8132856 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8132856 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2632220 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2632220 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 143613 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 143613 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 496781 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150336 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8132856 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3445434 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12225407 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 496781 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150336 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8132856 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3445434 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12225407 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 19778 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9507 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 29285 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 216104 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 216104 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 189953 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 189953 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1753 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6630 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5167 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021851 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.938416 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 486850576 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 486850576 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 506555 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 152150 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 658705 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3098065 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3098065 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 11055157 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 11055157 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815552 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 815552 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8406399 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 8406399 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2722472 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2722472 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 157346 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 157346 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 506555 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 152150 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 8406399 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3538024 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 12603128 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 506555 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 152150 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8406399 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3538024 # number of overall hits +system.cpu1.l2cache.overall_hits::total 12603128 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20442 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9977 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 30419 # number of ReadReq misses +system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses +system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 219088 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 219088 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194583 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 194583 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 231177 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 231177 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700002 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 700002 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 932644 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 932644 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250983 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 250983 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 19778 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9507 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 700002 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1163821 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1893108 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 19778 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9507 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 700002 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1163821 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1893108 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 605384500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 346513000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 951897500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 912243000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 912243000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 268121000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 268121000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1526000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1526000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10578569498 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10578569498 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24914386500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24914386500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33296141988 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33296141988 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 300579500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 300579500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 605384500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 346513000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24914386500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43874711486 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 69740995486 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 605384500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 346513000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24914386500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43874711486 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 69740995486 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 516559 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159843 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 676402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3051311 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3051311 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 10695223 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 10695223 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 216106 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 216106 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189953 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 189953 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241398 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 241398 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700129 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 700129 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 948287 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 948287 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 259232 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 259232 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20442 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9977 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 700129 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1189685 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1920233 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20442 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9977 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 700129 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1189685 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1920233 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 617018000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 362407000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 979425000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 937065000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 937065000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273754000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273754000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1804499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1804499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10806413996 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 10806413996 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24362152500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24362152500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33291553995 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33291553995 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 509000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 509000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 617018000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 362407000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24362152500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 44097967991 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 69439545491 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 617018000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 362407000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24362152500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 44097967991 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 69439545491 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 526997 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 162127 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 689124 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3098065 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3098065 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 11055158 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 11055158 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219089 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 219089 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194584 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 194584 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1044391 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1044391 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8832858 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 8832858 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3564864 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3564864 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 394596 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 394596 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 516559 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159843 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 8832858 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4609255 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 14118515 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 516559 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159843 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 8832858 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4609255 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 14118515 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059477 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.043295 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999991 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999991 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1056950 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1056950 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9106528 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 9106528 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3670759 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3670759 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416578 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 416578 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 526997 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 162127 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 9106528 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4727709 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 14523361 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 526997 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 162127 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 9106528 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4727709 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 14523361 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061538 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.044142 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999995 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221351 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.221351 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.079250 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.079250 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.261621 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.261621 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.636051 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.636051 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059477 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079250 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252497 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.134087 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059477 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079250 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252497 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.134087 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36448.196066 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32504.609869 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4221.314737 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4221.314737 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1411.512321 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1411.512321 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 508666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 508666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45759.610593 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45759.610593 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35591.879023 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35591.879023 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35700.805439 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35700.805439 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1197.609001 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1197.609001 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 36839.417237 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 36839.417237 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228391 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228391 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076882 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076882 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258335 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258335 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622289 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622289 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061538 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076882 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251641 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.132217 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061538 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076882 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251641 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.132217 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36324.245765 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32197.804004 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4277.116958 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4277.116958 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1406.875215 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1406.875215 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 601499.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601499.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44765.963247 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44765.963247 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34796.662472 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34796.662472 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35107.044592 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35107.044592 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1.963492 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1.963492 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 36162.041529 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 36162.041529 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 43184 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1062517 # number of writebacks -system.cpu1.l2cache.writebacks::total 1062517 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 15 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 83 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6377 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 6377 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 790 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 790 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 15 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 83 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7167 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 7267 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 15 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 83 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7167 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 7267 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 19763 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9424 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 29187 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 714287 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 216104 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 216104 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 189953 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 189953 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.unused_prefetches 43998 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1082545 # number of writebacks +system.cpu1.l2cache.writebacks::total 1082545 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 17 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 90 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6036 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 6036 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 724 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 724 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 17 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 90 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6760 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 6871 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 17 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 90 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6760 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 6871 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20425 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9887 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 30312 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 721434 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 219088 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 219088 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194583 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194583 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224800 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 224800 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700000 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700000 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 931854 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 931854 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250982 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250982 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 19763 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9424 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700000 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1156654 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1885841 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 19763 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9424 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700000 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1156654 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2600128 # number of overall MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235362 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 235362 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700125 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700125 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 947563 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 947563 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 259229 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 259229 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20425 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9887 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700125 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1182925 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1913362 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20425 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9887 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700125 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1182925 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2634796 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7278 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7063 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14787 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 288576500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 775021000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30894742332 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4083186496 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4083186496 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2906568497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2906568497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1292000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1292000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8335690998 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8335690998 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20714350500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20714350500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27592853988 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27592853988 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6684154500 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6684154500 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 288576500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20714350500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35928544986 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 57417916486 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 288576500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20714350500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35928544986 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 88312658818 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9064500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860524000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 869588500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9064500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860524000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 869588500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043150 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14250 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 301606000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 795670000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29780460685 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4150846499 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4150846499 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2983943996 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2983943996 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1522499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1522499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8542642996 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8542642996 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20161321500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20161321500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27488554995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27488554995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6032275000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6032275000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 301606000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20161321500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36031197991 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 56988189491 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 301606000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20161321500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36031197991 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 86768650176 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 826904500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 835747000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8842500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 826904500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 835747000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043986 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999991 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999991 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215245 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215245 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079250 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261400 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261400 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.636048 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.636048 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133572 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222680 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222680 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076882 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258138 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258138 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.622282 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.622282 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.131744 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184164 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 28307892 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14471357 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1579 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 577788 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 577774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 765944 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13251577 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7509 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7509 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4119049 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 10696803 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1405207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 907922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 426575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 466317 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1072889 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1050772 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8832858 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4591457 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 449471 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 394596 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26498252 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15919614 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339109 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1095958 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43852933 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1130579136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615678398 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1278736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4132472 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1751668742 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5086460 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75030592 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 19865784 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.045122 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.207576 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181418 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 29139456 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14890637 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1736 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 592017 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 591980 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 37 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 780515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13649954 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7187 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7187 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4195318 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11056894 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1429217 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 912059 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 423433 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 478761 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1089502 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1063784 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9106528 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4703864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 480825 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 417736 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27319260 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16358508 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 344119 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1118457 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 45140344 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1165608768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 632082996 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1297016 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4215976 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1803204756 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5174570 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 77236160 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 20377107 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.044844 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.206971 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18969410 95.49% 95.49% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 896360 4.51% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 19463345 95.52% 95.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 913725 4.48% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 37 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19865784 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 28134048478 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20377107 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 28962136490 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171886209 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181919759 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13252138560 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13662646557 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7328947477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7521057995 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 179350830 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 182080323 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 579510776 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 591562794 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40272 # Transaction distribution -system.iobus.trans_dist::ReadResp 40272 # Transaction distribution -system.iobus.trans_dist::WriteReq 136595 # Transaction distribution -system.iobus.trans_dist::WriteResp 136595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136646 # Transaction distribution +system.iobus.trans_dist::WriteResp 136645 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47799 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2455,13 +2465,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231144 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231144 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122681 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353963 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2474,103 +2484,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496318 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42593000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496722 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42736003 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 316000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 316501 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25879501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25813003 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34434000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34441500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569469195 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569849738 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92646000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92766000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147840000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115567 # number of replacements -system.iocache.tags.tagsinuse 11.304352 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115581 # number of replacements +system.iocache.tags.tagsinuse 11.283387 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115583 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9167343261000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.387949 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.916404 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.461747 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244775 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706522 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9167357489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841167 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.442220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240073 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465139 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705212 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040505 # Number of tag accesses -system.iocache.tags.data_accesses 1040505 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040766 # Number of tag accesses +system.iocache.tags.data_accesses 1040766 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115572 # number of demand (read+write) misses -system.iocache.demand_misses::total 115612 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115601 # number of demand (read+write) misses +system.iocache.demand_misses::total 115641 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115572 # number of overall misses -system.iocache.overall_misses::total 115612 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1979797452 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1984993952 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115601 # number of overall misses +system.iocache.overall_misses::total 115641 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5212500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1870801980 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1876014480 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13211000243 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13211000243 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15190797695 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15196363195 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15190797695 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15196363195 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13212782258 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13212782258 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5581500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15083584238 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15089165738 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5581500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15083584238 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15089165738 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115572 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115612 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115601 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115641 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115572 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115612 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115601 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115641 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2584,53 +2594,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 223510.184889 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 210551.569024 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123781.952655 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131442.784443 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131442.784443 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 49739 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123798.649445 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130482.836866 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130482.836866 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 43615 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3574 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.916900 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.338048 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106693 # number of writebacks system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115572 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115612 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115601 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115641 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115572 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115612 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537597452 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1540943952 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115601 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115641 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3362500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1427151980 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1430514480 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7865666947 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7865666947 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9403264399 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9406829899 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9403264399 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9406829899 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7870696448 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7870696448 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3581500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9297848428 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9301429928 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3581500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9297848428 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9301429928 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2644,661 +2654,655 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160842.103009 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 160551.569024 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1396284 # number of replacements -system.l2c.tags.tagsinuse 65138.751942 # Cycle average of tags in use -system.l2c.tags.total_refs 7016729 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1457215 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.815164 # Average number of references to valid blocks. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73745.375609 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73745.375609 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1414426 # number of replacements +system.l2c.tags.tagsinuse 65137.583571 # Cycle average of tags in use +system.l2c.tags.total_refs 6994560 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1476169 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.738319 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10857.852094 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.720367 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 194.423316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4494.530949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16342.707209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9582.831884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.988799 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 269.731759 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4576.542600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8162.860696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.165678 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002967 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.068581 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.249370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146222 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.069832 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.124555 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.155633 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993938 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9763 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50927 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 80 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9269 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4645 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44789 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.148972 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.777084 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 77350226 # Number of tag accesses -system.l2c.tags.data_accesses 77350226 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2692321 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2692321 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 204225 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 155483 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 359708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 52320 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 51074 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 103394 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55531 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 51791 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107322 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13410 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5332 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 636242 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 595342 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315678 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10946 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4404 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 639193 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 560416 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 301207 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3082170 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 138800 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 132737 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 271537 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 13410 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5332 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 636242 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 650873 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 315678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10946 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4404 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 639193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 612207 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 301207 # number of demand (read+write) hits -system.l2c.demand_hits::total 3189492 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 13410 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5332 # number of overall hits -system.l2c.overall_hits::cpu0.inst 636242 # number of overall hits -system.l2c.overall_hits::cpu0.data 650873 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 315678 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10946 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4404 # number of overall hits -system.l2c.overall_hits::cpu1.inst 639193 # number of overall hits -system.l2c.overall_hits::cpu1.data 612207 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 301207 # number of overall hits -system.l2c.overall_hits::total 3189492 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 22618 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 28127 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 50745 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 499 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 689 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1188 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 80171 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 45173 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125344 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1777 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 61929 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 136966 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 215441 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1460 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 60807 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 104797 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 773882 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 449504 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 106576 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 556080 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1994 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1777 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 61929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 217137 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 215441 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1649 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1460 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 60807 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 149970 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) misses -system.l2c.demand_misses::total 899226 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1994 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1777 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61929 # number of overall misses -system.l2c.overall_misses::cpu0.data 217137 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 215441 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1649 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1460 # number of overall misses -system.l2c.overall_misses::cpu1.inst 60807 # number of overall misses -system.l2c.overall_misses::cpu1.data 149970 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 187062 # number of overall misses -system.l2c.overall_misses::total 899226 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 166509500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 180855500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 347365000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6105500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8200500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 14306000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8647457500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4904092500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13551550000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 211493000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 194819500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6896332000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15165548000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 166890000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 150626500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6689940000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 12141260000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 97864036626 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 46615500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 36764000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 83379500 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 211493000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 194819500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6896332000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23813005500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 166890000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 150626500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6689940000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 17045352500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 111415586626 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 211493000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 194819500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6896332000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23813005500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 166890000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 150626500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6689940000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 17045352500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of overall miss cycles -system.l2c.overall_miss_latency::total 111415586626 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2692321 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2692321 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 226843 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 183610 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 410453 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 52819 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 51763 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 104582 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 135702 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 96964 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 232666 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15404 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7109 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 698171 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 732308 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 531119 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12595 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5864 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 700000 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 665213 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 488269 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3856052 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 588304 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 239313 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 827617 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 15404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 698171 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 868010 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 531119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12595 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5864 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 700000 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 762177 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 488269 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4088718 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 15404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 698171 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 868010 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 531119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12595 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5864 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 700000 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 762177 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 488269 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4088718 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.099708 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.153189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.123632 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.009447 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.013311 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.011360 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.590787 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.465874 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.538729 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.249965 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.088702 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187033 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.248977 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086867 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.157539 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.200693 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.764068 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.445341 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.671905 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.249965 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.088702 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.250155 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.248977 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.086867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196765 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.219929 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.249965 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.088702 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.250155 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.248977 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.086867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196765 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.219929 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7361.813600 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6429.960536 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6845.304956 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12235.470942 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11902.031930 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 12042.087542 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107862.662309 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108562.470945 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 108114.867884 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 109633.933596 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 111358.684946 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110724.909832 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103168.835616 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110019.241206 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115855.034018 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 126458.603025 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 103.704305 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 344.955712 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 149.941555 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 123901.651672 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 123901.651672 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 622 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 11569.884492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 195.527132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 189.575172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5571.537349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16752.169298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 243.722413 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 247.067471 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3668.697792 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7415.172357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9157.755820 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.176542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002893 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.085015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.255618 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.154518 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003719 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003770 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.113147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.139736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993921 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10627 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 250 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50866 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 764 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9737 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44783 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.162155 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003815 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.776154 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 76792424 # Number of tag accesses +system.l2c.tags.data_accesses 76792424 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2702608 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2702608 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 192434 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 150964 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 343398 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 50257 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 52778 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 103035 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55782 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52105 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107887 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13231 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5451 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 616225 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 581799 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 304510 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10640 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4481 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 647147 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 570987 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 311044 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3065515 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 124497 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 122676 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 247173 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5451 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 616225 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 637581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 304510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 647147 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 623092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 311044 # number of demand (read+write) hits +system.l2c.demand_hits::total 3173402 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 13231 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5451 # number of overall hits +system.l2c.overall_hits::cpu0.inst 616225 # number of overall hits +system.l2c.overall_hits::cpu0.data 637581 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 304510 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10640 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4481 # number of overall hits +system.l2c.overall_hits::cpu1.inst 647147 # number of overall hits +system.l2c.overall_hits::cpu1.data 623092 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 311044 # number of overall hits +system.l2c.overall_hits::total 3173402 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 19140 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 25859 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 44999 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 523 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 682 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 81279 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 45582 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 126861 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1999 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 72224 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 145719 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1517 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 52978 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 99810 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 787476 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 432248 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 85316 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 517564 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2187 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1999 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 72224 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 226998 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1644 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1517 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 52978 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 145392 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) misses +system.l2c.demand_misses::total 914337 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2187 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1999 # number of overall misses +system.l2c.overall_misses::cpu0.inst 72224 # number of overall misses +system.l2c.overall_misses::cpu0.data 226998 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 234962 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1644 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1517 # number of overall misses +system.l2c.overall_misses::cpu1.inst 52978 # number of overall misses +system.l2c.overall_misses::cpu1.data 145392 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 174436 # number of overall misses +system.l2c.overall_misses::total 914337 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 159938500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 143600000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 303538500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6591000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8923000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 15514000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8642428000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4940577000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 13583005000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 231505500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 211185500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7798644500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 15829133000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 165185000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 157137500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6014742000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 11671652500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 99292357724 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 231505500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 211185500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 7798644500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 24471561000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 165185000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 157137500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6014742000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 16612229500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 112875362724 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 231505500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 211185500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 7798644500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 24471561000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 165185000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 157137500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6014742000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 16612229500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of overall miss cycles +system.l2c.overall_miss_latency::total 112875362724 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2702608 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2702608 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 211574 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 176823 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 388397 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 50780 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 53460 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 104240 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 137061 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 97687 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 234748 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15418 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7450 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 688449 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 727518 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 539472 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12284 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5998 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 700125 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 670797 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 485480 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3852991 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 556745 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 207992 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 764737 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 15418 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7450 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 688449 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 864579 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 539472 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12284 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5998 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 700125 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 768484 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 485480 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4087739 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 15418 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7450 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 688449 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 864579 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 539472 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12284 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5998 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 700125 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 768484 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 485480 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4087739 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090465 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.146242 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.115858 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010299 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012757 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.011560 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.593013 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.466613 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540414 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.268322 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104908 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200296 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.252918 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.148793 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.204380 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.776384 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.410189 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.676787 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.268322 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.104908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.262553 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.252918 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.189193 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.223678 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.268322 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.104908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.262553 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.252918 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.189193 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.223678 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 8356.243469 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5553.192312 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6745.449899 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12602.294455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13083.577713 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 12874.688797 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 106330.392844 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108388.771884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 107069.982106 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105645.572786 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107978.573604 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 108627.790473 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103584.377060 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113532.824946 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116938.708546 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 126089.376342 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 123450.503178 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 123450.503178 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 12 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 51.833333 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1054868 # number of writebacks -system.l2c.writebacks::total 1054868 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 132 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 14 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 311 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 132 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 132 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 311 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 56418 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 56418 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 22618 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 28127 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 50745 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 499 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 689 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1188 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 80171 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 45173 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 125344 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1777 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 61790 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 136941 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1460 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60675 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 104783 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 773571 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 449504 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 106576 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 556080 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1994 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1777 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 61790 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 217112 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1649 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1460 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 60675 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 149956 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 898915 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1994 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1777 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 61790 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 217112 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1649 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1460 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 60675 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 149956 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 898915 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1064634 # number of writebacks +system.l2c.writebacks::total 1064634 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 107 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 22 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 137 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 289 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 107 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 137 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 107 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 137 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 289 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 58693 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 58693 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 19140 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 25859 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 44999 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 523 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 682 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1205 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 81279 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 45582 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 126861 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1999 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72117 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 145697 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1517 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 52841 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 99787 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 787187 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 432248 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 85316 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 517564 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2187 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1999 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 72117 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 226976 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1644 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1517 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 52841 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 145369 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 914048 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2187 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1999 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 72117 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 226976 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1644 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1517 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 52841 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 145369 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 914048 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7181 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 90772 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38264 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6966 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 90895 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38388 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14690 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 129036 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 461841000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 578903500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1040744500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 11863000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16565000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 28428000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7845723550 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4452337552 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 12298061102 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 177048502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6267361033 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13793559696 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 136026500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6069566554 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11092033207 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 90099351689 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9394175000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2170818500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 11564993500 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 177048502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 6267361033 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21639283246 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 136026500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 6069566554 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 15544370759 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 102397412791 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 177048502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 6267361033 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21639283246 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 136026500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 6069566554 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 15544370759 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 102397412791 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14153 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 129283 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 389704500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 525466000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 915170500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12566500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16471000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 29037500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7829611555 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4484731054 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 12314342609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 191194502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7068927036 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14369749705 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141966502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5474322057 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10671015209 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 91394456852 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8929441001 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1642247000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 10571688001 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 191194502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 7068927036 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22199361260 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141966502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5474322057 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 15155746263 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 103708799461 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 191194502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 7068927036 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22199361260 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141966502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5474322057 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 15155746263 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 103708799461 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5226952503 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7066500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 731143001 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 9610531504 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5267143505 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6847500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 701418504 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 9620779009 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5226952503 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7066500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731143001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9610531504 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5267143505 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6847500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701418504 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9620779009 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.099708 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.153189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.123632 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.009447 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.013311 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011360 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590787 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465874 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.538729 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186999 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157518 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200612 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.764068 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.445341 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.671905 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.219853 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.219853 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090465 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.146242 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.115858 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010299 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012757 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011560 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593013 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466613 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540414 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200266 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.148759 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.204305 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.776384 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.410189 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.676787 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.223607 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.223607 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20360.736677 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.430024 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20337.574168 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24027.724665 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24151.026393 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24097.510373 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 96330.067484 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98388.202668 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 97069.569127 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 98627.629292 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106937.929881 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116102.599321 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20658.143013 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19248.991983 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20425.856514 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3616665 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2148581 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2925 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3622014 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2135906 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2993 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 90772 # Transaction distribution -system.membus.trans_dist::ReadResp 873224 # Transaction distribution -system.membus.trans_dist::WriteReq 38264 # Transaction distribution -system.membus.trans_dist::WriteResp 38264 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1161561 # Transaction distribution -system.membus.trans_dist::CleanEvict 250705 # Transaction distribution -system.membus.trans_dist::UpgradeReq 347946 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 273520 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 90895 # Transaction distribution +system.membus.trans_dist::ReadResp 886992 # Transaction distribution +system.membus.trans_dist::WriteReq 38388 # Transaction distribution +system.membus.trans_dist::WriteResp 38387 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1171327 # Transaction distribution +system.membus.trans_dist::CleanEvict 257625 # Transaction distribution +system.membus.trans_dist::UpgradeReq 339183 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 279038 # Transaction distribution system.membus.trans_dist::UpgradeResp 24 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 139972 # Transaction distribution -system.membus.trans_dist::ReadExResp 124377 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 782452 # Transaction distribution -system.membus.trans_dist::InvalidateReq 660097 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122510 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 141595 # Transaction distribution +system.membus.trans_dist::ReadExResp 126059 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 796097 # Transaction distribution +system.membus.trans_dist::InvalidateReq 636810 # Transaction distribution +system.membus.trans_dist::InvalidateResp 29788 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122681 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4392225 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4540373 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4778460 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4412900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4561541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4799816 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128305664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 128513860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7270464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 135784324 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 584171 # Total snoops (count) -system.membus.snoopTraffic 172608 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2333030 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013166 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113984 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129909760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 130118772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7279744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 137398516 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 631660 # Total snoops (count) +system.membus.snoopTraffic 165184 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2322011 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014128 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.118018 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2302314 98.68% 98.68% # Request fanout histogram -system.membus.snoop_fanout::1 30716 1.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2289206 98.59% 98.59% # Request fanout histogram +system.membus.snoop_fanout::1 32805 1.41% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2333030 # Request fanout histogram -system.membus.reqLayer0.occupancy 103320999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2322011 # Request fanout histogram +system.membus.reqLayer0.occupancy 103411493 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21353996 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21687499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8035790677 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8057234059 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5121349382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5202386097 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45284261 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 79808698 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3341,78 +3345,79 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12127091 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6563266 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2068389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 180040 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 163507 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 16533 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 90774 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4717359 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3747189 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2956256 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 703976 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 376914 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1080890 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 286236 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 286236 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4627139 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 855379 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 827617 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9817286 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8000729 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17818015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243574806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194096942 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 437671748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2816292 # Total snoops (count) -system.toL2Bus.snoopTraffic 120259472 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8375094 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.374182 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.487973 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12161965 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6407928 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2357892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 209457 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 187271 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 22186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 90897 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4728170 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38388 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38387 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3767242 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2958537 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 681779 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382073 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1063852 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289918 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289918 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4637675 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 890912 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 871981 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9721848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8056306 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17778154 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 242672912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 195596708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 438269620 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2964469 # Total snoops (count) +system.toL2Bus.snoopTraffic 121867728 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8426211 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.390204 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493164 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5257818 62.78% 62.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3100743 37.02% 99.80% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 16533 0.20% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5160452 61.24% 61.24% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3243573 38.49% 99.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 22186 0.26% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8375094 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9230074402 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8426211 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9265268057 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2547405 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 8336972 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4495965489 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4478456950 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3978820805 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4027071928 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 5d6718d90..6bb63026a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.688775 # Number of seconds simulated -sim_ticks 51688774990000 # Number of ticks simulated -final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.688741 # Number of seconds simulated +sim_ticks 51688741391000 # Number of ticks simulated +final_tick 51688741391000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 278192 # Simulator instruction rate (inst/s) -host_op_rate 326870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15185295340 # Simulator tick rate (ticks/s) -host_mem_usage 686764 # Number of bytes of host memory used -host_seconds 3403.87 # Real time elapsed on the host -sim_insts 946928269 # Number of instructions simulated -sim_ops 1112623169 # Number of ops (including micro ops) simulated +host_inst_rate 269524 # Simulator instruction rate (inst/s) +host_op_rate 316717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14692427127 # Simulator tick rate (ticks/s) +host_mem_usage 686428 # Number of bytes of host memory used +host_seconds 3518.05 # Real time elapsed on the host +sim_insts 948199503 # Number of instructions simulated +sim_ops 1114227092 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory -system.physmem.bytes_read::total 76755656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 396416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 330752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10254464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65885128 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 402816 # Number of bytes read from this memory +system.physmem.bytes_read::total 77269576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10254464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10254464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 94159808 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 93636516 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 94180388 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6194 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 160226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1029468 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6294 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1207350 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1471247 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1473820 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1274651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1494901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1821670 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1199320 # Number of read requests accepted -system.physmem.writeReqs 1465322 # Number of write requests accepted -system.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue -system.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1822068 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1821670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1275050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3316969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1207350 # Number of read requests accepted +system.physmem.writeReqs 1473820 # Number of write requests accepted +system.physmem.readBursts 1207350 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1473820 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 77222592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 47808 # Total number of bytes read from write queue +system.physmem.bytesWritten 94178368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 77269576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 94180388 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70144 # Per bank write bursts -system.physmem.perBankRdBursts::1 74650 # Per bank write bursts -system.physmem.perBankRdBursts::2 68418 # Per bank write bursts -system.physmem.perBankRdBursts::3 68145 # Per bank write bursts -system.physmem.perBankRdBursts::4 72367 # Per bank write bursts -system.physmem.perBankRdBursts::5 76479 # Per bank write bursts -system.physmem.perBankRdBursts::6 68140 # Per bank write bursts -system.physmem.perBankRdBursts::7 71247 # Per bank write bursts -system.physmem.perBankRdBursts::8 66581 # Per bank write bursts -system.physmem.perBankRdBursts::9 125666 # Per bank write bursts -system.physmem.perBankRdBursts::10 74635 # Per bank write bursts -system.physmem.perBankRdBursts::11 76739 # Per bank write bursts -system.physmem.perBankRdBursts::12 72169 # Per bank write bursts -system.physmem.perBankRdBursts::13 75530 # Per bank write bursts -system.physmem.perBankRdBursts::14 66172 # Per bank write bursts -system.physmem.perBankRdBursts::15 71551 # Per bank write bursts -system.physmem.perBankWrBursts::0 89120 # Per bank write bursts -system.physmem.perBankWrBursts::1 91694 # Per bank write bursts -system.physmem.perBankWrBursts::2 88427 # Per bank write bursts -system.physmem.perBankWrBursts::3 87889 # Per bank write bursts -system.physmem.perBankWrBursts::4 92386 # Per bank write bursts -system.physmem.perBankWrBursts::5 94711 # Per bank write bursts -system.physmem.perBankWrBursts::6 88472 # Per bank write bursts -system.physmem.perBankWrBursts::7 91239 # Per bank write bursts -system.physmem.perBankWrBursts::8 88274 # Per bank write bursts -system.physmem.perBankWrBursts::9 94990 # Per bank write bursts -system.physmem.perBankWrBursts::10 92874 # Per bank write bursts -system.physmem.perBankWrBursts::11 94799 # Per bank write bursts -system.physmem.perBankWrBursts::12 93039 # Per bank write bursts -system.physmem.perBankWrBursts::13 95949 # Per bank write bursts -system.physmem.perBankWrBursts::14 87664 # Per bank write bursts -system.physmem.perBankWrBursts::15 91512 # Per bank write bursts +system.physmem.perBankRdBursts::0 73856 # Per bank write bursts +system.physmem.perBankRdBursts::1 76732 # Per bank write bursts +system.physmem.perBankRdBursts::2 71137 # Per bank write bursts +system.physmem.perBankRdBursts::3 69219 # Per bank write bursts +system.physmem.perBankRdBursts::4 73839 # Per bank write bursts +system.physmem.perBankRdBursts::5 75948 # Per bank write bursts +system.physmem.perBankRdBursts::6 69505 # Per bank write bursts +system.physmem.perBankRdBursts::7 70913 # Per bank write bursts +system.physmem.perBankRdBursts::8 66486 # Per bank write bursts +system.physmem.perBankRdBursts::9 126372 # Per bank write bursts +system.physmem.perBankRdBursts::10 74130 # Per bank write bursts +system.physmem.perBankRdBursts::11 75275 # Per bank write bursts +system.physmem.perBankRdBursts::12 69111 # Per bank write bursts +system.physmem.perBankRdBursts::13 75650 # Per bank write bursts +system.physmem.perBankRdBursts::14 65166 # Per bank write bursts +system.physmem.perBankRdBursts::15 73264 # Per bank write bursts +system.physmem.perBankWrBursts::0 92929 # Per bank write bursts +system.physmem.perBankWrBursts::1 92717 # Per bank write bursts +system.physmem.perBankWrBursts::2 91280 # Per bank write bursts +system.physmem.perBankWrBursts::3 89601 # Per bank write bursts +system.physmem.perBankWrBursts::4 92792 # Per bank write bursts +system.physmem.perBankWrBursts::5 94531 # Per bank write bursts +system.physmem.perBankWrBursts::6 90574 # Per bank write bursts +system.physmem.perBankWrBursts::7 91937 # Per bank write bursts +system.physmem.perBankWrBursts::8 87601 # Per bank write bursts +system.physmem.perBankWrBursts::9 94297 # Per bank write bursts +system.physmem.perBankWrBursts::10 91232 # Per bank write bursts +system.physmem.perBankWrBursts::11 93669 # Per bank write bursts +system.physmem.perBankWrBursts::12 91213 # Per bank write bursts +system.physmem.perBankWrBursts::13 96164 # Per bank write bursts +system.physmem.perBankWrBursts::14 87189 # Per bank write bursts +system.physmem.perBankWrBursts::15 93811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 468 # Number of times write queue was full causing retry -system.physmem.totGap 51688773130000 # Total gap between requests +system.physmem.numWrRetry 476 # Number of times write queue was full causing retry +system.physmem.totGap 51688739531000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1199305 # Read request sizes (log2) +system.physmem.readPktSize::6 1207335 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1462749 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1471247 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1136082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,184 +160,186 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 79220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 85555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 88116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 84810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 88690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 87321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 89133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 88726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 87724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 84525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 83639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 82667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 80351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 80396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1031 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 665465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.565125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.597276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 293.769616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 284377 42.73% 42.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 171033 25.70% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61820 9.29% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34355 5.16% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24207 3.64% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15228 2.29% 88.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11511 1.73% 90.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9122 1.37% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 53812 8.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 665465 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.563805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.518145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77523 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 77525 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77525 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.981451 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.132244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.585951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 65037 83.89% 83.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3875 5.00% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3091 3.99% 92.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2418 3.12% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1125 1.45% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 202 0.26% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 259 0.33% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 156 0.20% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 148 0.19% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 64 0.08% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 86 0.11% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 78 0.10% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 560 0.72% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 82 0.11% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 101 0.13% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.10% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 43 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 18 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 7 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads -system.physmem.totQLat 38956691672 # Total ticks spent queuing -system.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77525 # Writes before turning the bus around for reads +system.physmem.totQLat 38963077638 # Total ticks spent queuing +system.physmem.totMemAccLat 61586883888 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6033015000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32291.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51041.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 929087 # Number of row buffer hits during reads -system.physmem.writeRowHits 1069644 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes -system.physmem.avgGap 19398017.87 # Average gap between requests -system.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.244086 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states -system.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states -system.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states -system.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.324450 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states -system.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states -system.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 27.17 # Average write queue length when enqueuing +system.physmem.readRowHits 937085 # Number of row buffer hits during reads +system.physmem.writeRowHits 1075589 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.09 # Row buffer hit rate for writes +system.physmem.avgGap 19278426.78 # Average gap between requests +system.physmem.pageHitRate 75.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2387508900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1268991075 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4149403860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3843804420 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50777254320.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43920274980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3215166720 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 97172465130 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 73954032000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12292934061825 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12573646841220 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.256974 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51583978414040 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5941628250 # Time in different power states +system.physmem_0.memoryStateTime::REF 21591460000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51178312983500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 192588592528 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77208837210 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 213097889512 # Time in different power states +system.physmem_1.actEnergy 2363918340 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1256448600 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4465741560 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3837618720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51996700080.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 45282427920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3208431840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 99358559340 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 75199350240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12290630942340 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12577622785650 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.333895 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51581032449783 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5840657750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22110720000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51167308964000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 195831815407 # Time in different power states +system.physmem_1.memoryStateTime::ACT 79757518717 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 217891715126 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -354,30 +356,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261505306 # Number of BP lookups -system.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130159045 # Number of BTB hits +system.cpu.branchPred.lookups 261998834 # Number of BP lookups +system.cpu.branchPred.condPredicted 182856277 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12304668 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193336179 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130354436 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.423716 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31812925 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2139415 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7174940 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5106056 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2068884 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 846506 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -407,65 +409,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 574319 # Table walker walks requested -system.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 578626 # Table walker walks requested +system.cpu.dtb.walker.walksLong 578626 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22326 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190823 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 578626 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 578626 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 578626 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213149 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25594.731854 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21754.484647 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18075.189624 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 210684 98.84% 98.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2067 0.97% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 93 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 125 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 100 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 34 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213149 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 190824 89.53% 89.53% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22326 10.47% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213150 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 578626 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 578626 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213150 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213150 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 791776 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 182769858 # DTB read hits -system.cpu.dtb.read_misses 473161 # DTB read misses -system.cpu.dtb.write_hits 162201881 # DTB write hits -system.cpu.dtb.write_misses 101158 # DTB write misses +system.cpu.dtb.read_hits 182986827 # DTB read hits +system.cpu.dtb.read_misses 476580 # DTB read misses +system.cpu.dtb.write_hits 162437421 # DTB write hits +system.cpu.dtb.write_misses 102046 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80100 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1397 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15136 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183243019 # DTB read accesses -system.cpu.dtb.write_accesses 162303039 # DTB write accesses +system.cpu.dtb.perms_faults 23302 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183463407 # DTB read accesses +system.cpu.dtb.write_accesses 162539467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 344971739 # DTB hits -system.cpu.dtb.misses 574319 # DTB misses -system.cpu.dtb.accesses 345546058 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 345424248 # DTB hits +system.cpu.dtb.misses 578626 # DTB misses +system.cpu.dtb.accesses 346002874 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -495,70 +497,70 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 135751 # Table walker walks requested -system.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 136092 # Table walker walks requested +system.cpu.itb.walker.walksLong 136092 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118204 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136092 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136092 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136092 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119268 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28638.176208 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24049.001367 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 28797.920728 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116455 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2388 2.00% 99.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 112 0.09% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 99 0.08% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 153 0.13% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119268 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118204 99.11% 99.11% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1064 0.89% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119268 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136092 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136092 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 452655900 # ITB inst hits -system.cpu.itb.inst_misses 135751 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119268 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119268 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 255360 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 453450761 # ITB inst hits +system.cpu.itb.inst_misses 136092 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57496 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 333218 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 452791651 # ITB inst accesses -system.cpu.itb.hits 452655900 # DTB hits -system.cpu.itb.misses 135751 # DTB misses -system.cpu.itb.accesses 452791651 # DTB accesses -system.cpu.numPwrStateTransitions 33180 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 453586853 # ITB inst accesses +system.cpu.itb.hits 453450761 # DTB hits +system.cpu.itb.misses 136092 # DTB misses +system.cpu.itb.accesses 453586853 # DTB accesses +system.cpu.numPwrStateTransitions 33202 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16601 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3037201042.152340 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59610606886.622597 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7303 43.99% 43.99% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9263 55.80% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state @@ -570,601 +572,598 @@ system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2530699433 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988777738856 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16601 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1268166890229 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50420574500771 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2536387791 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 946928269 # Number of instructions committed -system.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.672536 # CPI: cycles per instruction -system.cpu.ipc 0.374177 # IPC: instructions per cycle +system.cpu.committedInsts 948199503 # Number of instructions committed +system.cpu.committedOps 1114227092 # Number of ops (including micro ops) committed +system.cpu.discardedOps 98303819 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7741 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100842203450 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.674952 # CPI: cycles per instruction +system.cpu.ipc 0.373839 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction -system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::IntAlu 772296777 69.31% 69.31% # Class of committed instruction +system.cpu.op_class_0::IntMult 2306158 0.21% 69.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 98958 0.01% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatAdd 8 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCmp 13 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCvt 21 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatMultAcc 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 108989 0.01% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::MemRead 177200146 15.93% 85.46% # Class of committed instruction -system.cpu.op_class_0::MemWrite 160983743 14.47% 99.93% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 112460 0.01% 99.94% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 664876 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 108924 0.01% 69.54% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::MemRead 177418599 15.92% 85.46% # Class of committed instruction +system.cpu.op_class_0::MemWrite 161212850 14.47% 99.93% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 115060 0.01% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 669723 0.06% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1112623169 # Class of committed instruction +system.cpu.op_class_0::total 1114227092 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed -system.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked -system.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11091024 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16601 # number of quiesce instructions executed +system.cpu.tickCycles 1794953387 # Number of cycles that the object actually ticked +system.cpu.idleCycles 741434404 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11118153 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954086 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329643971 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11118665 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.647801 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954086 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits -system.cpu.dcache.overall_hits::total 320875829 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1383364255 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1383364255 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 168779255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168779255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151620030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151620030 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 521599 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 521599 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337919 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337919 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018497 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4018497 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4332994 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4332994 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 320737204 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320737204 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321258803 # number of overall hits +system.cpu.dcache.overall_hits::total 321258803 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6105244 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6105244 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4304073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4304073 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1482683 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1482683 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1242865 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1242865 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 316228 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 316228 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses -system.cpu.dcache.overall_misses::total 13097731 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 11652182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11652182 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13134865 # number of overall misses +system.cpu.dcache.overall_misses::total 13134865 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107444842500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107444842500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 170230992500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 170230992500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27308613500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27308613500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5074922000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5074922000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 303646309500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 303646309500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 303646309500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 303646309500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 174693570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 174693570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 155704542 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 155704542 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1994973 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1994973 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580475 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1580475 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4320727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4320727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4318997 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4318997 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 331978587 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 331978587 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 333973560 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 333973560 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034878 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034878 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738724 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.738724 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786579 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786579 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072842 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072842 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 304984448500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 304984448500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 304984448500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 304984448500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 174884499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 174884499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 155924103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 155924103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004282 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2004282 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580784 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1580784 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4334725 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4334725 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4332995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4332995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 332389386 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 332389386 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 334393668 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 334393668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034910 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034910 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027604 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.739758 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.739758 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786233 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786233 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072952 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039218 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039218 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035056 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035056 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039280 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039280 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.779426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.779426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39551.139700 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39551.139700 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21972.308738 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21972.308738 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16048.300593 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16048.300593 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26122.368719 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23183.123054 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26174.020325 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26174.020325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23219.458175 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23219.458175 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8512101 # number of writebacks -system.cpu.dcache.writebacks::total 8512101 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 311042 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 311042 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1897692 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1897692 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70889 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70889 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2208886 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2208886 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2208886 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2208886 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5781994 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5781994 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2390100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2390100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466271 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1466271 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1243016 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1243016 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 243840 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 243840 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8530547 # number of writebacks +system.cpu.dcache.writebacks::total 8530547 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315482 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 315482 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904891 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1904891 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 158 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 158 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70720 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70720 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2220531 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2220531 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2220531 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2220531 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5789762 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5789762 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2399182 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2399182 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1475215 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1475215 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1242707 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1242707 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 245508 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 245508 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9415110 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9415110 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10881381 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10881381 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9431651 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9431651 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10906866 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10906866 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94938379000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 94938379000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89047691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89047691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25686251500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25686251500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26061179000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26061179000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3474287500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3474287500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 210047249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 210047249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 235733500500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 235733500500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6230847500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6230847500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6230847500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6230847500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033106 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033106 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015387 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015387 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.736032 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.736032 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786133 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786133 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056638 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056638 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028375 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028375 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032617 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032617 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16397.630680 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16397.630680 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37115.854904 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37115.854904 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17411.869795 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17411.869795 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20971.298142 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20971.298142 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14151.422764 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14151.422764 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24547500 # number of replacements +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.464524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.464524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21613.312248 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21613.312248 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184913.565408 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184913.565408 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92441.693990 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92441.693990 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24600209 # number of replacements system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 428505873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24600721 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.418427 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 21430954500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses -system.cpu.icache.tags.data_accesses 476870138 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits -system.cpu.icache.overall_hits::total 427774095 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24548022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24548022 # number of overall misses -system.cpu.icache.overall_misses::total 24548022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329750158000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329750158000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329750158000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329750158000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329750158000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 452322117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 452322117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 452322117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 452322117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 452322117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 452322117 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency +system.cpu.icache.tags.tag_accesses 477707334 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477707334 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 428505873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428505873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428505873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428505873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428505873 # number of overall hits +system.cpu.icache.overall_hits::total 428505873 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24600731 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24600731 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24600731 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24600731 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24600731 # number of overall misses +system.cpu.icache.overall_misses::total 24600731 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330486746500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330486746500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330486746500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330486746500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330486746500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330486746500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 453106604 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 453106604 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 453106604 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 453106604 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 453106604 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 453106604 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054293 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054293 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054293 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054293 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054293 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054293 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13434.021391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13434.021391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13434.021391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13434.021391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24547500 # number of writebacks -system.cpu.icache.writebacks::total 24547500 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24548022 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24548022 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24548022 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24548022 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24548022 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24548022 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 24600209 # number of writebacks +system.cpu.icache.writebacks::total 24600209 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24600731 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24600731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24600731 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24600731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24600731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24600731 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 305202137000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305202137000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305886016500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 305886016500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305886016500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 305886016500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305886016500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 305886016500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054293 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054293 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054293 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12434.021432 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12434.021432 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1591901 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.549959 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 69520908 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1655396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.996542 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1601564 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65405.294347 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 69675530 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1664947 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 41.848497 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6255171000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9036.958133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 433.683776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 402.305370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7871.756997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.137893 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006617 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120113 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.727293 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998055 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 790 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56108 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.964722 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 582399864 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 582399864 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921588 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 261482 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1183070 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8512101 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8512101 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24543775 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 24543775 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 29573 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 29573 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1660508 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1660508 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24440962 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 24440962 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7164937 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7164937 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 700668 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 700668 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 921588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 261482 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24440962 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8825445 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34449477 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 921588 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 261482 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24440962 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8825445 # number of overall hits -system.cpu.l2cache.overall_hits::total 34449477 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6273 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5180 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 11453 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4073 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4073 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 9201.337762 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 431.981496 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 403.879639 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8049.770162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47318.325288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.140401 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122830 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.722020 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5965 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56053 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963226 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 583673795 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 583673795 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 260236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1181712 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8530547 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8530547 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 24596465 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 24596465 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 29651 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 29651 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1663600 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1663600 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24492767 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24492767 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7181719 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7181719 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 699060 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 699060 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 921476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 260236 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24492767 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8845319 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34519798 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 921476 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 260236 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24492767 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8845319 # number of overall hits +system.cpu.l2cache.overall_hits::total 34519798 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6194 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5168 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 11362 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4020 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4020 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 696158 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 696158 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107059 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 107059 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 326956 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 326956 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 542348 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 542348 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6273 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5180 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 107059 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1023114 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1141626 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6273 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5180 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 107059 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1023114 # number of overall misses -system.cpu.l2cache.overall_misses::total 1141626 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 939749000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 683365000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1623114000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72777000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 72777000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 702193 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 702193 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107963 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 107963 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328484 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 328484 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 543647 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 543647 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6194 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 107963 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1030677 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1150002 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6194 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5168 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 107963 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1030677 # number of overall misses +system.cpu.l2cache.overall_misses::total 1150002 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 927255500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 692143500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1619399000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72892500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 72892500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66999821500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66999821500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11524194500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11524194500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37120013000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 37120013000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 2135500 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 2135500 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 939749000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 683365000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11524194500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 104119834500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 117267143000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 939749000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 683365000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11524194500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 104119834500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 117267143000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927861 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 266662 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1194523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8512101 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8512101 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 24543775 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 24543775 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33646 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 33646 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67521066500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 67521066500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11586638500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11586638500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37187085000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 37187085000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 927255500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 692143500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11586638500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 104708151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 117914189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 927255500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 692143500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11586638500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 104708151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 117914189000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927670 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 265404 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1193074 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8530547 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8530547 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 24596465 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 24596465 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33671 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 33671 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2356666 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2356666 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24548021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 24548021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7491893 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7491893 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1243016 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1243016 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927861 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 266662 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 24548021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9848559 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35591103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927861 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 266662 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24548021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9848559 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35591103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006761 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.009588 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.121055 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.121055 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2365793 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2365793 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24600730 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 24600730 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7510203 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7510203 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1242707 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1242707 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927670 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 265404 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 24600730 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9875996 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 35669800 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927670 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 265404 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24600730 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9875996 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 35669800 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006677 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.009523 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119391 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119391 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.295400 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.295400 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004361 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004361 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043641 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043641 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.436316 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.436316 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006761 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019425 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004361 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.103885 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.032076 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006761 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019425 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004361 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.103885 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.032076 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296811 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.296811 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004389 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004389 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043738 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043738 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437470 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.437470 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006677 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019472 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004389 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.104362 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.032240 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006677 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019472 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004389 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.104362 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.032240 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149702.211818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133928.695820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 142527.635980 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18132.462687 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18132.462687 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 3.937509 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 3.937509 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 102719.404604 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 102719.404604 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96157.418972 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96157.418972 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107320.457008 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107320.457008 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113208.208010 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113208.208010 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 102533.899071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 102533.899071 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1356118 # number of writebacks -system.cpu.l2cache.writebacks::total 1356118 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1364616 # number of writebacks +system.cpu.l2cache.writebacks::total 1364616 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6273 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5180 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 11453 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6194 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5168 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 11362 # number of ReadReq MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4073 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4073 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4020 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4020 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 696158 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 696158 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107056 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107056 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 326935 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 326935 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 542348 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 542348 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6273 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5180 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 107056 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1023093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1141602 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6273 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5180 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 107056 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1023093 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1141602 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 702193 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 702193 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107961 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107961 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328463 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328463 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 543647 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 543647 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 107961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1030656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1149979 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6194 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 107961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1030656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1149979 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85987 # number of ReadReq MSHR uncacheable @@ -1173,156 +1172,156 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119694 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 877019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 631565000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1508584000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77761500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77761500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 865315500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 640463500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1505779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76760000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60038241001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60038241001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10453433004 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10453433004 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33849413548 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33849413548 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11199554001 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11199554001 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 877019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 631565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10453433004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93887654549 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 877019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 631565000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10453433004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93887654549 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60499136001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60499136001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10506850003 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10506850003 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33899524045 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33899524045 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11224464501 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11224464501 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 865315500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 640463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10506850003 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 94398660046 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 106411289049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 865315500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 640463500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10506850003 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 94398660046 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 106411289049 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3611009000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809783000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420792000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809544500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420553500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3611009000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809544500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420553500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119391 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119391 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296811 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296811 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004389 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437470 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437470 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032240 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032240 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132527.635980 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19094.527363 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19094.527363 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86157.418261 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86157.418261 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97320.791795 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97320.791795 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103206.522637 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103206.522637 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20646.604324 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20646.604324 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172410.508666 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109557.880842 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86191.185852 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78705.311043 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 72189026 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 36469595 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1946 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1780354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33892071 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9895163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24600209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2824554 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 33674 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2114439 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 33675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2365793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2365793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24600731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7513010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1271678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1242738 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73906251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33558527 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2215155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 110352219 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3152206656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1178259346 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2123232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7421360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4340010594 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2135457 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 91396008 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 39200512 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134637 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38476553 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 723959 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 39200512 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 69790374998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1501881 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36983722099 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15503705051 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 406910942 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1287502964 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40334 # Transaction distribution +system.iobus.trans_dist::ReadResp 40334 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1339,11 +1338,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353810 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1358,16 +1357,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37695500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 339500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1385,26 +1384,26 @@ system.iobus.reqLayer16.occupancy 16000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25148500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36444000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569308376 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147786000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115495 # number of replacements +system.iocache.tags.tagsinuse 10.448162 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13141692173000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519394 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy @@ -1412,48 +1411,48 @@ system.iocache.tags.occ_percent::total 0.653010 # Av system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039974 # Number of tag accesses +system.iocache.tags.data_accesses 1039974 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8886 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses -system.iocache.demand_misses::total 115544 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115513 # number of demand (read+write) misses +system.iocache.demand_misses::total 115553 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115504 # number of overall misses -system.iocache.overall_misses::total 115544 # number of overall misses +system.iocache.overall_misses::realview.ide 115513 # number of overall misses +system.iocache.overall_misses::total 115553 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2011459152 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2016544652 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13390572724 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13390572724 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15402031876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15407468376 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15402031876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15407468376 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8886 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115513 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115553 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115513 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115553 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1468,52 +1467,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227309.204656 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 226935.027234 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125539.757781 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125539.757781 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133336.809741 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133336.809741 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51202 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3365 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.216048 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8886 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115513 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115553 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115513 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115553 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1569009152 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1572244652 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8051866391 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8051866391 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9620875543 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9624312043 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9620875543 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9624312043 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1528,94 +1527,95 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177309.204656 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 176935.027234 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75488.134619 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75488.134619 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3529625 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1749962 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 85987 # Transaction distribution -system.membus.trans_dist::ReadResp 540308 # Transaction distribution +system.membus.trans_dist::ReadResp 542659 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution -system.membus.trans_dist::CleanEvict 243530 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4703 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1471247 # Transaction distribution +system.membus.trans_dist::CleanEvict 244702 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4583 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 695596 # Transaction distribution -system.membus.trans_dist::ReadExResp 695596 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution -system.membus.trans_dist::InvalidateReq 648947 # Transaction distribution +system.membus.trans_dist::ReadExReq 701633 # Transaction distribution +system.membus.trans_dist::ReadExResp 701633 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 456672 # Transaction distribution +system.membus.trans_dist::InvalidateReq 650311 # Transaction distribution +system.membus.trans_dist::InvalidateResp 28814 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4556598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4686250 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237342 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237342 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4923592 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2899 # Total snoops (count) -system.membus.snoopTraffic 185088 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1923263 # Request fanout histogram -system.membus.snoop_fanout::mean 0.016618 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164222764 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164393170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7227200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7227200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 171620370 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 32071 # Total snoops (count) +system.membus.snoopTraffic 208000 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1932895 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016796 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.128505 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram -system.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1900431 98.32% 98.32% # Request fanout histogram +system.membus.snoop_fanout::1 32464 1.68% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1923263 # Request fanout histogram -system.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1932895 # Request fanout histogram +system.membus.reqLayer0.occupancy 99728500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5568000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9720767792 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6477610584 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 75150025 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1658,28 +1658,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index e5ad0fb86..37952af83 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384924 # Number of seconds simulated -sim_ticks 47384923997000 # Number of ticks simulated -final_tick 47384923997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384940 # Number of seconds simulated +sim_ticks 47384940455000 # Number of ticks simulated +final_tick 47384940455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222565 # Simulator instruction rate (inst/s) -host_op_rate 253955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9938840366 # Simulator tick rate (ticks/s) -host_mem_usage 775220 # Number of bytes of host memory used -host_seconds 4767.65 # Real time elapsed on the host -sim_insts 1061113479 # Number of instructions simulated -sim_ops 1210768532 # Number of ops (including micro ops) simulated +host_inst_rate 206357 # Simulator instruction rate (inst/s) +host_op_rate 242664 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10614318936 # Simulator tick rate (ticks/s) +host_mem_usage 793572 # Number of bytes of host memory used +host_seconds 4464.25 # Real time elapsed on the host +sim_insts 921230293 # Number of instructions simulated +sim_ops 1083311023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 111296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 112064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3744224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13424584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13993600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 28480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2827552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 6560336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5891392 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory -system.physmem.bytes_read::total 47171096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3744224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2827552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6571776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65473344 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 222656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 215552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4481312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16941064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21659840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 116096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2978912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10395024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12881984 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 421760 # Number of bytes read from this memory +system.physmem.bytes_read::total 70394200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4481312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2978912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7460224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86479488 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65493928 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 74456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 209772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 218650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 102518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 92053 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory -system.physmem.num_reads::total 753070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1023021 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86500072 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 264717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 338435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 46589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 162435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 201281 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6590 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1115931 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1351242 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1025595 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 79017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 283309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 295318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 138448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 124331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 995487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 79017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59672 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 138689 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1381734 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1353816 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 94572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 357520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 457104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 62866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 271858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1485582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 94572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 157439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1825042 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1382168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1381734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 79017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 283743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 295318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 138448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 124331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2377655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 753070 # Number of read requests accepted -system.physmem.writeReqs 1025595 # Number of write requests accepted -system.physmem.readBursts 753070 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1025595 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 48174848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 65493376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 47171096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65493928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1825476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1825042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 94572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 357954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 457104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 271858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3311058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1115931 # Number of read requests accepted +system.physmem.writeReqs 1353816 # Number of write requests accepted +system.physmem.readBursts 1115931 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1353816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 71392384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27200 # Total number of bytes read from write queue +system.physmem.bytesWritten 86499392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70394200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 86500072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 46580 # Per bank write bursts -system.physmem.perBankRdBursts::1 53938 # Per bank write bursts -system.physmem.perBankRdBursts::2 49260 # Per bank write bursts -system.physmem.perBankRdBursts::3 49621 # Per bank write bursts -system.physmem.perBankRdBursts::4 42595 # Per bank write bursts -system.physmem.perBankRdBursts::5 51807 # Per bank write bursts -system.physmem.perBankRdBursts::6 43920 # Per bank write bursts -system.physmem.perBankRdBursts::7 48776 # Per bank write bursts -system.physmem.perBankRdBursts::8 40673 # Per bank write bursts -system.physmem.perBankRdBursts::9 65073 # Per bank write bursts -system.physmem.perBankRdBursts::10 36606 # Per bank write bursts -system.physmem.perBankRdBursts::11 43439 # Per bank write bursts -system.physmem.perBankRdBursts::12 41245 # Per bank write bursts -system.physmem.perBankRdBursts::13 45785 # Per bank write bursts -system.physmem.perBankRdBursts::14 46575 # Per bank write bursts -system.physmem.perBankRdBursts::15 46839 # Per bank write bursts -system.physmem.perBankWrBursts::0 64495 # Per bank write bursts -system.physmem.perBankWrBursts::1 70494 # Per bank write bursts -system.physmem.perBankWrBursts::2 68186 # Per bank write bursts -system.physmem.perBankWrBursts::3 67192 # Per bank write bursts -system.physmem.perBankWrBursts::4 60923 # Per bank write bursts -system.physmem.perBankWrBursts::5 66733 # Per bank write bursts -system.physmem.perBankWrBursts::6 61182 # Per bank write bursts -system.physmem.perBankWrBursts::7 63809 # Per bank write bursts -system.physmem.perBankWrBursts::8 61319 # Per bank write bursts -system.physmem.perBankWrBursts::9 65628 # Per bank write bursts -system.physmem.perBankWrBursts::10 58470 # Per bank write bursts -system.physmem.perBankWrBursts::11 62975 # Per bank write bursts -system.physmem.perBankWrBursts::12 59380 # Per bank write bursts -system.physmem.perBankWrBursts::13 62220 # Per bank write bursts -system.physmem.perBankWrBursts::14 64833 # Per bank write bursts -system.physmem.perBankWrBursts::15 65495 # Per bank write bursts +system.physmem.perBankRdBursts::0 66640 # Per bank write bursts +system.physmem.perBankRdBursts::1 69755 # Per bank write bursts +system.physmem.perBankRdBursts::2 65507 # Per bank write bursts +system.physmem.perBankRdBursts::3 67407 # Per bank write bursts +system.physmem.perBankRdBursts::4 65920 # Per bank write bursts +system.physmem.perBankRdBursts::5 70505 # Per bank write bursts +system.physmem.perBankRdBursts::6 65125 # Per bank write bursts +system.physmem.perBankRdBursts::7 71371 # Per bank write bursts +system.physmem.perBankRdBursts::8 68061 # Per bank write bursts +system.physmem.perBankRdBursts::9 95897 # Per bank write bursts +system.physmem.perBankRdBursts::10 65782 # Per bank write bursts +system.physmem.perBankRdBursts::11 68970 # Per bank write bursts +system.physmem.perBankRdBursts::12 60174 # Per bank write bursts +system.physmem.perBankRdBursts::13 71971 # Per bank write bursts +system.physmem.perBankRdBursts::14 71235 # Per bank write bursts +system.physmem.perBankRdBursts::15 71186 # Per bank write bursts +system.physmem.perBankWrBursts::0 81261 # Per bank write bursts +system.physmem.perBankWrBursts::1 86034 # Per bank write bursts +system.physmem.perBankWrBursts::2 81926 # Per bank write bursts +system.physmem.perBankWrBursts::3 83311 # Per bank write bursts +system.physmem.perBankWrBursts::4 82546 # Per bank write bursts +system.physmem.perBankWrBursts::5 86081 # Per bank write bursts +system.physmem.perBankWrBursts::6 81799 # Per bank write bursts +system.physmem.perBankWrBursts::7 86537 # Per bank write bursts +system.physmem.perBankWrBursts::8 86254 # Per bank write bursts +system.physmem.perBankWrBursts::9 89944 # Per bank write bursts +system.physmem.perBankWrBursts::10 82817 # Per bank write bursts +system.physmem.perBankWrBursts::11 84554 # Per bank write bursts +system.physmem.perBankWrBursts::12 78968 # Per bank write bursts +system.physmem.perBankWrBursts::13 86566 # Per bank write bursts +system.physmem.perBankWrBursts::14 86628 # Per bank write bursts +system.physmem.perBankWrBursts::15 86327 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51084 # Number of times write queue was full causing retry -system.physmem.totGap 47384922418500 # Total gap between requests +system.physmem.numWrRetry 51513 # Number of times write queue was full causing retry +system.physmem.totGap 47384938876500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 731712 # Read request sizes (log2) +system.physmem.readPktSize::6 1094573 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1023021 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 370845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 159212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 67904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 21454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 19383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1351242 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 480312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 254385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 111988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,148 +189,147 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 21368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 29807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 34041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 37200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 39344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 42468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 48762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 52922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 55311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 53100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 53471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 56934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 54202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 50890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 25036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120369 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 764267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 148.727500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 100.859518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 194.434520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 493267 64.54% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 163474 21.39% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 41666 5.45% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17289 2.26% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12509 1.64% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7716 1.01% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5337 0.70% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4250 0.56% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18759 2.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 764267 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 44107 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.065908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 84.736057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 44102 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 22318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 42386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 51611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 68066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 77080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 84175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 91218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 81081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 75935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120772 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1035166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 152.526679 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.371009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.170623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 664281 64.17% 64.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 215041 20.77% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 59106 5.71% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25397 2.45% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20542 1.98% 95.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11502 1.11% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7604 0.73% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6193 0.60% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25500 2.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1035166 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 63814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.480459 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 70.581857 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 63808 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 44107 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 44107 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.201170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.952947 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 661.116222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-2047 44104 99.99% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 44107 # Writes before turning the bus around for reads -system.physmem.totQLat 41283708010 # Total ticks spent queuing -system.physmem.totMemAccLat 55397433010 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3763660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 54845.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 63814 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 63814 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.179569 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.530322 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 597.849869 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 63812 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 63814 # Writes before turning the bus around for reads +system.physmem.totQLat 67332860089 # Total ticks spent queuing +system.physmem.totMemAccLat 88248597589 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5577530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 60360.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 73595.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 79110.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing -system.physmem.readRowHits 561323 # Number of row buffer hits during reads -system.physmem.writeRowHits 450469 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 44.02 # Row buffer hit rate for writes -system.physmem.avgGap 26640723.47 # Average gap between requests -system.physmem.pageHitRate 56.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2854700520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1517297925 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2759588580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2730133080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29211995280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 33494587950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1472320320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 56725165950 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 41153148000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11302922668065 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11474856149160 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.162595 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47307603847909 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 2604858642 # Time in different power states -system.physmem_0.memoryStateTime::REF 12408932000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47076037433500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 107169572536 # Time in different power states -system.physmem_0.memoryStateTime::ACT 62306306199 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 124396894123 # Time in different power states -system.physmem_1.actEnergy 2602215840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1383095340 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2614917900 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2611670400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28356416400.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 34195829880 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1463733600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 50772105900 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 40848981120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11305996104720 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11470859465250 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.078250 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47306089548027 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2606555105 # Time in different power states -system.physmem_1.memoryStateTime::REF 12048152000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47088369465500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 106377666151 # Time in different power states -system.physmem_1.memoryStateTime::ACT 64179741868 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 111342416376 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing +system.physmem.readRowHits 837889 # Number of row buffer hits during reads +system.physmem.writeRowHits 593994 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.95 # Row buffer hit rate for writes +system.physmem.avgGap 19186151.00 # Average gap between requests +system.physmem.pageHitRate 58.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3662384460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1946584530 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3871522200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3494763900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31929318720.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 40834926540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1598586240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 62046559410 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 43455299520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11294770338285 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11487626755995 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.432018 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47291190900816 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2771331378 # Time in different power states +system.physmem_0.memoryStateTime::REF 13558872000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47041958774500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 113164787559 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77419210306 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 136067479257 # Time in different power states +system.physmem_1.actEnergy 3728772180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1981870440 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4093190640 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3560342760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33599910240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42188393820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1621939680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 66725147910 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 45519792000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11290481164380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11493516343440 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.556311 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47288162727367 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2732090205 # Time in different power states +system.physmem_1.memoryStateTime::REF 14267508000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47023294872500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 118540781222 # Time in different power states +system.physmem_1.memoryStateTime::ACT 79778077178 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 146327125895 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -357,30 +356,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 171085788 # Number of BP lookups -system.cpu0.branchPred.condPredicted 118750961 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6834189 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 131203024 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 82797286 # Number of BTB hits +system.cpu0.branchPred.lookups 139151101 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91634411 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6732234 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97916993 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61670085 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 63.106233 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18455974 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 190741 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4318211 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2658051 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1660160 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 412902 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 62.982005 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19220371 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 194045 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4187621 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2676103 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1511518 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 384250 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,89 +409,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 532616 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 532616 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9645 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81431 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 247073 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 285543 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2264.919819 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12542.152959 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 283669 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1336 0.47% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 422 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 12 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 608743 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 608743 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13705 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96942 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 292908 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 315835 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2627.591939 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 312900 99.07% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2131 0.67% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 548 0.17% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 139 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 285543 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 266524 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21513.586019 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.741629 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18436.018606 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 263851 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1863 0.70% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 357 0.13% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 245 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 96 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 28 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 57 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 266524 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 526829631640 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.594347 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.546107 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 525653507140 99.78% 99.78% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 581220000 0.11% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 279235500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 118625000 0.02% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 95795000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 61233500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16684500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 22309000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 986000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 526829631640 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 81432 89.41% 89.41% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9645 10.59% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 91077 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 532616 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 315835 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 324732 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 320100 98.57% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3009 0.93% 99.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 694 0.21% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 681 0.21% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 132 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 68 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 324732 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 522550016344 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.577122 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.559179 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 521035310844 99.71% 99.71% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 819753000 0.16% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 323762500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 144297000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 115791000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 61783500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 19805000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 28515500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 990500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 522550016344 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 96943 87.61% 87.61% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13705 12.39% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 110648 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 608743 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 532616 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 91077 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 608743 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110648 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 91077 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 623693 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 719391 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 121664189 # DTB read hits -system.cpu0.dtb.read_misses 378617 # DTB read misses -system.cpu0.dtb.write_hits 79494049 # DTB write hits -system.cpu0.dtb.write_misses 153999 # DTB write misses +system.cpu0.dtb.read_hits 101564011 # DTB read hits +system.cpu0.dtb.read_misses 439385 # DTB read misses +system.cpu0.dtb.write_hits 82403711 # DTB write hits +system.cpu0.dtb.write_misses 169358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36225 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 277 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5846 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 43119 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 431 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7683 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 36132 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 122042806 # DTB read accesses -system.cpu0.dtb.write_accesses 79648048 # DTB write accesses +system.cpu0.dtb.perms_faults 39881 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 102003396 # DTB read accesses +system.cpu0.dtb.write_accesses 82573069 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 201158238 # DTB hits -system.cpu0.dtb.misses 532616 # DTB misses -system.cpu0.dtb.accesses 201690854 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 183967722 # DTB hits +system.cpu0.dtb.misses 608743 # DTB misses +system.cpu0.dtb.accesses 184576465 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -522,1186 +521,1187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 84620 # Table walker walks requested -system.cpu0.itb.walker.walksLong 84620 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60290 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9899 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 74721 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1224.749401 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11693.335691 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 74465 99.66% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 211 0.28% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 17 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 13 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74721 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71253 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25715.211991 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22899.199736 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22689.495972 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 69781 97.93% 97.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 978 1.37% 99.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 312 0.44% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 90 0.13% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 23 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 85247 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85247 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1031 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58619 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10594 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 74653 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1640.215397 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 74120 99.29% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 439 0.59% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 37 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 19 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 19 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74653 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 70244 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 67750 96.45% 96.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1764 2.51% 98.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 417 0.59% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 170 0.24% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 42 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 26 0.04% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71253 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 385068972872 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.863923 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.343128 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52431106232 13.62% 13.62% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 332607446140 86.38% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 28719500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1617500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 83500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 385068972872 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 60290 98.27% 98.27% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1064 1.73% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61354 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 70244 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 419443065740 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.871284 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.335229 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 54034549916 12.88% 12.88% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 365365302324 87.11% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 40992500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2004000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 217000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 419443065740 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58619 98.27% 98.27% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1031 1.73% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 59650 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84620 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84620 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85247 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85247 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61354 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61354 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 145974 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 247137553 # ITB inst hits -system.cpu0.itb.inst_misses 84620 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59650 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59650 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 144897 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 219469803 # ITB inst hits +system.cpu0.itb.inst_misses 85247 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26024 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31398 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 210277 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 204530 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 247222173 # ITB inst accesses -system.cpu0.itb.hits 247137553 # DTB hits -system.cpu0.itb.misses 84620 # DTB misses -system.cpu0.itb.accesses 247222173 # DTB accesses -system.cpu0.numPwrStateTransitions 10024 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 5012 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 9377758605.326616 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 105865716307.531311 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3741 74.64% 74.64% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1240 24.74% 99.38% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.40% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.48% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.52% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.36% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 219555050 # ITB inst accesses +system.cpu0.itb.hits 219469803 # DTB hits +system.cpu0.itb.misses 85247 # DTB misses +system.cpu0.itb.accesses 219555050 # DTB accesses +system.cpu0.numPwrStateTransitions 27212 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13606 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3453780783.684036 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 93985708249.621262 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3589 26.38% 26.38% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9986 73.39% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988782107984 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 5012 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 383597867103 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47001326129897 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 767196996 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 6914083139000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13606 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 392799112195 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 785608211 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 91423789 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 677610005 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 171085788 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 103911311 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 634233277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14647700 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1877525 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 301361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5874017 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 723644 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 823593 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 246927402 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1755267 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27806 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 742581056 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.048226 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.216568 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 89154333 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 616347679 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 139151101 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83566559 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 651741352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14592652 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2033431 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 298378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6056906 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 755254 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 834704 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 219265865 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1675112 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28029 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 758170684 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.951385 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.212910 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 362128339 48.77% 48.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 152866679 20.59% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 57232327 7.71% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 170353711 22.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 412487393 54.41% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 134584185 17.75% 72.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 46569297 6.14% 78.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 164529809 21.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 742581056 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.223001 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.883228 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 106308771 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 322958086 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 273818410 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 34299444 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5196345 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 25584090 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2168541 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 698124632 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23697866 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5196345 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 140217201 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48265126 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 214765524 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 273791275 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 60345585 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 681004210 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6177353 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9309706 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 255993 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 440694 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 28265124 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11577 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 651054888 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1024843126 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 780850511 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 751131 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 593650334 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 57404539 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14068671 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12084501 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 69307711 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 122420852 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82711928 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8893855 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7669271 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 660071199 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14190254 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 662533207 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2711266 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 53711593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34745859 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 272694 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 742581056 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.892203 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.090645 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 758170684 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.177125 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.784548 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 107249627 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 379334150 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 227390625 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 38947644 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5248638 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19981467 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2087891 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 636989334 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23191131 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5248638 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 143394034 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 56142021 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 253850770 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 229681319 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 69853902 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 619319594 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6178554 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10862186 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 388792 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 930621 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 33162716 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11693 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 591176589 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 957415604 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 731049781 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 649204 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 532948721 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58227868 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16256269 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14199870 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78279720 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101593087 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85666218 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9630459 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8075180 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 596126359 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16460453 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 601474893 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2699291 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54684336 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35421563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 283328 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 758170684 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.793324 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.057959 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 387058469 52.12% 52.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139937745 18.84% 70.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 131660547 17.73% 88.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76428143 10.29% 98.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7490821 1.01% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5331 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 428799597 56.56% 56.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139371286 18.38% 74.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 115828942 15.28% 90.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 66243104 8.74% 98.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7922364 1.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5391 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 742581056 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 758170684 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 66589128 48.32% 48.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 76488 0.06% 48.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 21054 0.02% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 7 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34108431 24.75% 73.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 36653931 26.60% 99.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 35680 0.03% 99.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 336881 0.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61955212 45.30% 45.30% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 62513 0.05% 45.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 16729 0.01% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 21 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36421436 26.63% 71.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 37996782 27.78% 99.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 31053 0.02% 99.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 287360 0.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 455471856 68.75% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1439073 0.22% 68.96% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 77169 0.01% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 52155 0.01% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 4 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 124717383 18.82% 87.81% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80374226 12.13% 99.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 54363 0.01% 99.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 346932 0.05% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 411361741 68.39% 68.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1567778 0.26% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 78948 0.01% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 39915 0.01% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 104723474 17.41% 86.08% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83352955 13.86% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 49350 0.01% 99.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 300687 0.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 662533207 # Type of FU issued -system.cpu0.iq.rate 0.863576 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 137821600 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.208022 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2206895899 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 727628917 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 645910972 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1284434 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 480253 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 448459 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 799528739 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 826049 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2613047 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 601474893 # Type of FU issued +system.cpu0.iq.rate 0.765617 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 136771106 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227393 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2099488112 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 667007258 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 583889559 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1102755 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 413748 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 385073 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 737537568 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 708401 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2768605 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12294694 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15978 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 137291 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5350030 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12684669 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17846 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 151274 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5522197 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2543221 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4059606 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2796342 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4797484 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5196345 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6516939 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1752683 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 674395512 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5248638 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8055865 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1895421 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 612718172 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 122420852 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82711928 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 11855960 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 50620 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1645630 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 137291 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1918568 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3145797 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5064365 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 654555035 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 121653240 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7451061 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 101593087 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85666218 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13907446 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58112 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1764578 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 151274 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1949210 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3085558 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5034768 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 593488019 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 101560351 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7385409 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 134059 # number of nop insts executed -system.cpu0.iew.exec_refs 201144943 # number of memory reference insts executed -system.cpu0.iew.exec_branches 144279686 # Number of branches executed -system.cpu0.iew.exec_stores 79491703 # Number of stores executed -system.cpu0.iew.exec_rate 0.853177 # Inst execution rate -system.cpu0.iew.wb_sent 647087647 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 646359431 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 309251056 # num instructions producing a value -system.cpu0.iew.wb_consumers 520070148 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.842495 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.594633 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 46740214 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 13917560 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4706684 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 733649612 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.845840 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.553610 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 131360 # number of nop insts executed +system.cpu0.iew.exec_refs 183963466 # number of memory reference insts executed +system.cpu0.iew.exec_branches 111638269 # Number of branches executed +system.cpu0.iew.exec_stores 82403115 # Number of stores executed +system.cpu0.iew.exec_rate 0.755450 # Inst execution rate +system.cpu0.iew.wb_sent 585082868 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 584274632 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284506732 # num instructions producing a value +system.cpu0.iew.wb_consumers 466304278 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.743723 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.610131 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 47796807 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16177125 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4684546 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 749065087 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.744798 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.551758 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 452365639 61.66% 61.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 136210339 18.57% 80.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 77415879 10.55% 90.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 24022740 3.27% 94.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12736407 1.74% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8516612 1.16% 96.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5825168 0.79% 97.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3494792 0.48% 98.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13062036 1.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 504468440 67.35% 67.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 127495809 17.02% 84.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53846196 7.19% 91.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 17894232 2.39% 93.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12874355 1.72% 95.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8922431 1.19% 96.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5996417 0.80% 97.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3594154 0.48% 98.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13973053 1.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 733649612 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 541241308 # Number of instructions committed -system.cpu0.commit.committedOps 620549845 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 749065087 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 475226157 # Number of instructions committed +system.cpu0.commit.committedOps 557902476 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 187488051 # Number of memory references committed -system.cpu0.commit.loads 110126156 # Number of loads committed -system.cpu0.commit.membars 3681828 # Number of memory barriers committed -system.cpu0.commit.branches 138866442 # Number of branches committed -system.cpu0.commit.fp_insts 440023 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 558745881 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13735984 # Number of function calls committed. +system.cpu0.commit.refs 169052439 # Number of memory references committed +system.cpu0.commit.loads 88908418 # Number of loads committed +system.cpu0.commit.membars 3969625 # Number of memory barriers committed +system.cpu0.commit.branches 106090436 # Number of branches committed +system.cpu0.commit.fp_insts 377224 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 511981133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14308761 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 431741221 69.57% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1213492 0.20% 69.77% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 61406 0.01% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 45675 0.01% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.79% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 110075333 17.74% 87.53% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77018370 12.41% 99.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 50823 0.01% 99.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 343525 0.06% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 387443640 69.45% 69.45% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1310567 0.23% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 61901 0.01% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 33929 0.01% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 88862033 15.93% 85.63% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 79847111 14.31% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 46385 0.01% 99.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 296910 0.05% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 620549845 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13062036 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1383927534 # The number of ROB reads -system.cpu0.rob.rob_writes 1343471696 # The number of ROB writes -system.cpu0.timesIdled 977066 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24615940 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94002651032 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 541241308 # Number of Instructions Simulated -system.cpu0.committedOps 620549845 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.417477 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.417477 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.705479 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.705479 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 749870098 # number of integer regfile reads -system.cpu0.int_regfile_writes 449143556 # number of integer regfile writes -system.cpu0.fp_regfile_reads 735783 # number of floating regfile reads -system.cpu0.fp_regfile_writes 351380 # number of floating regfile writes -system.cpu0.cc_regfile_reads 158312331 # number of cc regfile reads -system.cpu0.cc_regfile_writes 158973081 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1390796279 # number of misc regfile reads -system.cpu0.misc_regfile_writes 13965731 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5697124 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.351019 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 176571011 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5697636 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.990223 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 557902476 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13973053 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1336174255 # The number of ROB reads +system.cpu0.rob.rob_writes 1220466867 # The number of ROB writes +system.cpu0.timesIdled 1005352 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27437527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93984272695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 475226157 # Number of Instructions Simulated +system.cpu0.committedOps 557902476 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.653125 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.653125 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.604915 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.604915 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 700618930 # number of integer regfile reads +system.cpu0.int_regfile_writes 416450651 # number of integer regfile writes +system.cpu0.fp_regfile_reads 634669 # number of floating regfile reads +system.cpu0.fp_regfile_writes 293776 # number of floating regfile writes +system.cpu0.cc_regfile_reads 128889270 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129563151 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1347671553 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16172806 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6286438 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.582319 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 156315528 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6286950 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 24.863492 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.351019 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992873 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992873 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.582319 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946450 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946450 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 387310320 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 387310320 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 104266262 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 104266262 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67643317 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 67643317 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201589 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 201589 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 157769 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 157769 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1740953 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1740953 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1780734 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1780734 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 172067348 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 172067348 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 172268937 # number of overall hits -system.cpu0.dcache.overall_hits::total 172268937 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6301527 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6301527 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6793475 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 6793475 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634052 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 634052 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800857 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 800857 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 257653 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 257653 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 179906 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 179906 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13895859 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13895859 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14529911 # number of overall misses -system.cpu0.dcache.overall_misses::total 14529911 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95042221000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 95042221000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 131968145043 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 131968145043 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29372616680 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 29372616680 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3694169500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3694169500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4281937500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4281937500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3493500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3493500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 256382982723 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 256382982723 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 256382982723 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 256382982723 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 110567789 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 110567789 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74436792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74436792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 835641 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 835641 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 958626 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 958626 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998606 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1998606 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1960640 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1960640 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 185963207 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 185963207 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 186798848 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 186798848 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056992 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.056992 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091265 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.091265 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758761 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758761 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.835422 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.835422 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.128916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.128916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091759 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091759 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.074724 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.074724 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.077784 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.077784 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15082.411136 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15082.411136 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19425.720275 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19425.720275 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36676.481170 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36676.481170 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14337.770179 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14337.770179 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23800.971063 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23800.971063 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 351060755 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 351060755 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 82089512 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 82089512 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69232216 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69232216 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209823 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 209823 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173405 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 173405 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1868090 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1868090 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1930069 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1930069 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 151495133 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 151495133 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 151704956 # number of overall hits +system.cpu0.dcache.overall_hits::total 151704956 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7010414 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7010414 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7797174 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7797174 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 751824 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 751824 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 805427 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 805427 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 284725 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 284725 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 186829 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 186829 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15613015 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15613015 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16364839 # number of overall misses +system.cpu0.dcache.overall_misses::total 16364839 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 112159926000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 158052575270 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29573159898 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29573159898 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4301491500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4301491500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4484661500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4484661500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2134500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2134500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 299785661168 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 299785661168 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89099926 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89099926 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77029390 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77029390 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961647 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 961647 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 978832 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 978832 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2152815 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2152815 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2116898 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2116898 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 167108148 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 167108148 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 168069795 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 168069795 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078680 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078680 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101223 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.101223 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781809 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781809 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822845 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822845 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132257 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132257 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088256 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088256 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093431 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093431 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097369 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097369 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18450.315502 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18450.315502 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17645.186039 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17645.186039 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8869783 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19194961 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 737578 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 651751 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.025553 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.451372 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5697132 # number of writebacks -system.cpu0.dcache.writebacks::total 5697132 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3191836 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3191836 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5417328 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5417328 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4607 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4607 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132998 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132998 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8613771 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 8613771 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8613771 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 8613771 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3109691 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3109691 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1376147 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1376147 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 627210 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 627210 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796250 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 796250 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124655 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124655 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179906 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 179906 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5282088 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5282088 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5909298 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5909298 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16022 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17403 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33425 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44727315000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44727315000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29679279164 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29679279164 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15040987500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15040987500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28394000680 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28394000680 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1654283000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1654283000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4102116500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4102116500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3408500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3408500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102800594844 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 102800594844 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117841582344 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 117841582344 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2952800500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2952800500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2952800500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2952800500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750574 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750574 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830616 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830616 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062371 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062371 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091759 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091759 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028404 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028404 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031635 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14383.202382 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14383.202382 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21566.939552 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21566.939552 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23980.783948 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23980.783948 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35659.655485 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35659.655485 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13270.891661 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13270.891661 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22801.443532 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22801.443532 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8999058 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 24447381 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 751224 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 774000 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.979194 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 31.585764 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6286527 # number of writebacks +system.cpu0.dcache.writebacks::total 6286527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3589298 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3589298 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6265824 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6265824 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4129 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4129 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147493 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147493 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9859251 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9859251 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9859251 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9859251 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3421116 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3421116 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1531350 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1531350 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 745052 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 745052 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801298 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 801298 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 137232 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137232 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 186825 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 186825 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5753764 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5753764 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6498816 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6498816 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29615 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59306 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51678055000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51678055000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34197879948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34197879948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17704904500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17704904500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28602356899 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28602356899 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1885182000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1885182000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4297888500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4297888500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2082500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2082500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5594868000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5594868000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5594868000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5594868000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038396 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038396 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019880 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019880 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774767 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774767 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818627 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818627 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063745 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063745 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088254 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088254 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034431 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034431 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038667 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038667 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19462.113248 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19462.113248 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19941.722747 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19941.722747 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184296.623393 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184296.623393 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88341.077038 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88341.077038 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6253789 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960237 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 240286309 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6254301 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 38.419371 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960237 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5974428 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960293 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 212911456 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5974940 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.634074 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13477910000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960293 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 293 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 500053900 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 500053900 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 240286309 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 240286309 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 240286309 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 240286309 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 240286309 # number of overall hits -system.cpu0.icache.overall_hits::total 240286309 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6613282 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6613282 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6613282 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6613282 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6613282 # number of overall misses -system.cpu0.icache.overall_misses::total 6613282 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70780975211 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 70780975211 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 70780975211 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 70780975211 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 70780975211 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 70780975211 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 246899591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 246899591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 246899591 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 246899591 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 246899591 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 246899591 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.026785 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.026785 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.026785 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.026785 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.026785 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.026785 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10702.851506 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10702.851506 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10702.851506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10702.851506 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10321318 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2209 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 763925 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 444450377 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 444450377 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 212911456 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 212911456 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 212911456 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 212911456 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 212911456 # number of overall hits +system.cpu0.icache.overall_hits::total 212911456 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6326229 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6326229 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6326229 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6326229 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6326229 # number of overall misses +system.cpu0.icache.overall_misses::total 6326229 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70930890398 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 70930890398 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 70930890398 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 70930890398 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 70930890398 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 70930890398 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 219237685 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 219237685 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 219237685 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 219237685 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 219237685 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 219237685 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028856 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028856 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028856 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028856 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028856 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028856 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11212.191402 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11212.191402 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10513720 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1665 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 740505 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.510905 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 169.923077 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6253789 # number of writebacks -system.cpu0.icache.writebacks::total 6253789 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 358564 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 358564 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 358564 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 358564 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 358564 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 358564 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6254718 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6254718 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6254718 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6254718 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6254718 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6254718 # number of overall MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.198041 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 128.076923 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 5974428 # number of writebacks +system.cpu0.icache.writebacks::total 5974428 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351221 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 351221 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 351221 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 351221 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 351221 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 351221 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5975008 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5975008 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5975008 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5975008 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5975008 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5975008 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63975689306 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 63975689306 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63975689306 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 63975689306 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63975689306 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 63975689306 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63931230447 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 63931230447 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63931230447 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 63931230447 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63931230447 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 63931230447 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.025333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.025333 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.025333 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10228.389083 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027254 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027254 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027254 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7458642 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7464953 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 5714 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8714333 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8724211 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 8793 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1000455 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2364779 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15742.421414 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10647963 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2380148 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.473656 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15396.444809 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 43.122287 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 36.767067 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 266.087250 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.939724 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002632 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002244 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016241 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.960841 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 419 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14866 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 62 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 139 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 106 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1114037 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2711723 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15840.616895 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10811538 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2727125 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.964445 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2357982000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.308256 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.621063 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.237059 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.450517 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.947223 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002052 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001174 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016385 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.966835 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 381 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14929 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 93 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 95 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 984 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5812 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1898 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.025574 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 415506231 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 415506231 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 543348 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 189541 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 732889 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3712844 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3712844 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8236224 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8236224 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869040 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 869040 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5709661 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5709661 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2921433 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2921433 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213137 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 213137 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 543348 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 189541 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5709661 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3790473 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10233023 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 543348 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 189541 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5709661 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3790473 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10233023 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20175 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10263 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 30438 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 244720 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 244720 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 179898 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 179898 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270342 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 270342 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 544652 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 544652 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 938726 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 938726 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 581343 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 581343 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20175 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10263 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 544652 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1209068 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1784158 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20175 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10263 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 544652 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1209068 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1784158 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 624969500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 390263000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1015232500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 927455000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 927455000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 261460000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 261460000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3280500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3280500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15324669997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 15324669997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 19971642000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 19971642000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36150023478 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36150023478 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 295919000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 295919000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 624969500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 390263000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19971642000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 51474693475 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 72461567975 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 624969500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 390263000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19971642000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 51474693475 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 72461567975 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 563523 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 199804 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 763327 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3712844 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3712844 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8236224 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8236224 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244748 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 244748 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179900 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 179900 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1139382 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1139382 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6254313 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 6254313 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3860159 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3860159 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794480 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 794480 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 563523 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 199804 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6254313 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4999541 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12017181 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 563523 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 199804 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6254313 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4999541 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12017181 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051365 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.039875 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999886 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999886 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999989 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 499 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1082 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5719 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5657 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.023254 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.911194 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 427199165 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 427199165 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 602660 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185799 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 788459 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4096903 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4096903 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8161916 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8161916 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 32 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 986017 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 986017 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5386829 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5386829 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255809 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3255809 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 183461 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 183461 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 602660 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185799 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5386829 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4241826 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10417114 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 602660 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185799 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5386829 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4241826 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10417114 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 25200 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12620 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 37820 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257381 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 257381 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 186815 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 186815 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295278 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 295278 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 588130 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 588130 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1045192 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1045192 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 617837 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 617837 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 25200 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12620 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 588130 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1340470 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1966420 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 25200 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12620 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 588130 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1340470 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1966420 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 896455000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 597646500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1494101500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 982091000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 982091000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295025000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295025000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2003000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2003000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18413910498 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 18413910498 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22335302000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22335302000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43094995483 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43094995483 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 882000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 882000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 896455000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 597646500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22335302000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 61508905981 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 85338309481 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 896455000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 597646500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22335302000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 61508905981 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 85338309481 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 627860 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 198419 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 826279 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4096903 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4096903 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 8161916 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 8161916 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257413 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 257413 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 186820 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 186820 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1281295 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1281295 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5974959 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5974959 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4301001 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4301001 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 801298 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 801298 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 627860 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 198419 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5974959 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5582296 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12383534 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 627860 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 198419 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5974959 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5582296 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12383534 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.063603 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.045771 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999876 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999876 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999973 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999973 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237271 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237271 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.087084 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.087084 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243183 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243183 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731728 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731728 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051365 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.087084 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241836 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.148467 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051365 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.087084 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241836 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.148467 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38026.210660 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33354.113279 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3789.861883 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3789.861883 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1453.379137 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1453.379137 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 546750 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 546750 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56686.234462 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56686.234462 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36668.628776 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36668.628776 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38509.664671 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38509.664671 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 509.026513 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 509.026513 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38026.210660 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36668.628776 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42573.861416 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40613.873869 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38026.210660 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36668.628776 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42573.861416 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40613.873869 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230453 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230453 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098432 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098432 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243011 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243011 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771045 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771045 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.063603 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098432 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.240129 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.158793 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.063603 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098432 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.240129 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.158793 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47357.091918 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39505.592279 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3815.709007 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3815.709007 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1579.236143 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1579.236143 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 400600 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 400600 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62361.268019 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62361.268019 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37976.811249 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37976.811249 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41231.654551 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41231.654551 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 1.427561 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 1.427561 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 43397.803867 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 43397.803867 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 1100 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 45.833333 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 43433 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1509114 # number of writebacks -system.cpu0.l2cache.writebacks::total 1509114 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 106 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 285 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 391 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 13345 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 13345 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 4691 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 4691 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 106 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 285 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 18036 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 18429 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 106 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 285 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 18036 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 18429 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20069 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9978 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 30047 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 744254 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 744254 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 244720 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 244720 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 179898 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 179898 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 256997 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 256997 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 544650 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 544650 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 934035 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 934035 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 581341 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 581341 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20069 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9978 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 544650 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1191032 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1765729 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20069 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9978 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 544650 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1191032 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 744254 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2509983 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 49027 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1747264 # number of writebacks +system.cpu0.l2cache.writebacks::total 1747264 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 192 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 348 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 21118 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 21118 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5796 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5796 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 13 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 192 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 348 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26914 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 27458 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 192 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 348 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26914 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 27458 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 25008 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 12272 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 37280 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 914694 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257381 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257381 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 186815 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 186815 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274160 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 274160 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 588126 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 588126 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1039396 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1039396 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 617824 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 617824 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 25008 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 12272 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 588126 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1313556 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1938962 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 25008 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 12272 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 588126 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1313556 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2853656 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37315 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17403 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 50908 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 54718 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 325652000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 828111000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36749075781 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36749075781 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4570856487 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4570856487 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2749581992 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2749581992 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12067143997 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12067143997 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16703715500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16703715500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30202721978 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30202721978 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21448570498 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21448570498 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 325652000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16703715500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42269865975 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 59801692475 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 325652000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16703715500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42269865975 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36749075781 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 96550768256 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 80599 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 518427500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1261063000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57180143123 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4798228494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4798228494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2893409994 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2893409994 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1691000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1691000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13686705498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13686705498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18806492000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18806492000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36387650483 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36387650483 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21673087497 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21673087497 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 518427500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18806492000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 50074355981 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 70141910981 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 518427500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18806492000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 50074355981 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 127322054104 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2824191500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4691651500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5357476000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7224936000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2824191500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4691651500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039363 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5357476000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7224936000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045118 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999886 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999886 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999989 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999876 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999876 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999973 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999973 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.225558 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.225558 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087084 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241968 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241968 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.731725 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.731725 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.146934 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213971 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213971 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098432 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241664 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241664 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771029 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771029 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156576 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208866 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27560.521849 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49377.061838 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18677.903265 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18677.903265 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15284.116510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15284.116510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461750 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461750 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46954.415799 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46954.415799 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30668.714771 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32335.749707 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32335.749707 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36894.990200 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36894.990200 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33867.990204 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38466.702068 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230440 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338200 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338200 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176269.598053 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125730.979499 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 84493.388182 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85742.379107 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 24756799 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12708263 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2196 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 629051 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 629043 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 884546 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11093405 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 17403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 17403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5225908 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8238069 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1170453 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 945799 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 463366 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 326275 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 490425 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1168917 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1146769 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6254718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4769163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 850255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 794480 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18805406 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18368662 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 418571 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1191985 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 38784624 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 800859216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 691176446 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1598432 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4508184 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1498142278 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5240375 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 104025792 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 18364082 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.052502 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.223039 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 25418604 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13061865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 690419 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 690321 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 98 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 966476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11336947 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 29691 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29691 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5857040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8164049 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1344034 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1151380 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 469212 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 335795 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 509398 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1315239 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1289150 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5975008 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5298799 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 872203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 802449 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17966980 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20229549 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 416579 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1325266 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39938374 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 765101392 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 766341777 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1587352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5022880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1538053401 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5977120 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 119917960 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 19518051 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.053731 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.225509 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 17399941 94.75% 94.75% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 964133 5.25% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18469421 94.63% 94.63% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1048532 5.37% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 98 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 18364082 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24622778944 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19518051 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 25305808947 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 185315667 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 186983903 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9409532092 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 8989974042 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8142032744 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9049403091 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 219209106 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 218640527 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 629194022 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 698295209 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 166724968 # Number of BP lookups -system.cpu1.branchPred.condPredicted 126846962 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6061099 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 131629441 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 75453810 # Number of BTB hits +system.cpu1.branchPred.lookups 130931248 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87112041 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6567659 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91792654 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56129151 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.322898 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16000678 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 166104 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3768010 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2280408 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1487602 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 378018 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 61.147759 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17311793 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 174850 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4346649 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2655837 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1690812 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 417178 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1731,84 +1731,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 467692 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 467692 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8751 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70596 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 217424 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 250268 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2074.929675 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 11460.901897 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 248915 99.46% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 899 0.36% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 341 0.14% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 250268 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 236712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20830.925344 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18161.943529 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14226.641322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 235430 99.46% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1000 0.42% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 142 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 87 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 6 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 38 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 236712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 410863041148 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.552097 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.557280 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 409906147648 99.77% 99.77% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 459057000 0.11% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 219368000 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 102318000 0.02% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 84455000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 58029500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 14454500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 18772000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 430000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 410863041148 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 70596 88.97% 88.97% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8751 11.03% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 79347 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 467692 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 551219 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 551219 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11436 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86181 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 255688 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 295531 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2259.422869 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 293454 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1395 0.47% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 424 0.14% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 50 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 295531 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 283173 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 281324 99.35% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1404 0.50% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 195 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 146 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 283173 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 475307081088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.614132 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.549956 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 474122952588 99.75% 99.75% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 603814500 0.13% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 247441500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 130616500 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 93327500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 62495500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 19627500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 26354000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 445000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 475307081088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86181 88.28% 88.28% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11436 11.72% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97617 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 551219 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 467692 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 79347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 551219 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97617 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 79347 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 547039 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 648836 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 135065828 # DTB read hits -system.cpu1.dtb.read_misses 329885 # DTB read misses -system.cpu1.dtb.write_hits 69791052 # DTB write hits -system.cpu1.dtb.write_misses 137807 # DTB write misses +system.cpu1.dtb.read_hits 95947338 # DTB read hits +system.cpu1.dtb.read_misses 376138 # DTB read misses +system.cpu1.dtb.write_hits 79464123 # DTB write hits +system.cpu1.dtb.write_misses 175081 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36136 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 592 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4990 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35142 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 372 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6075 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 39336 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 135395713 # DTB read accesses -system.cpu1.dtb.write_accesses 69928859 # DTB write accesses +system.cpu1.dtb.perms_faults 39563 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 96323476 # DTB read accesses +system.cpu1.dtb.write_accesses 79639204 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 204856880 # DTB hits -system.cpu1.dtb.misses 467692 # DTB misses -system.cpu1.dtb.accesses 205324572 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 175411461 # DTB hits +system.cpu1.dtb.misses 551219 # DTB misses +system.cpu1.dtb.accesses 175962680 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1838,1181 +1842,1180 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 78571 # Table walker walks requested -system.cpu1.itb.walker.walksLong 78571 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 897 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57010 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9455 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 69116 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 778.444933 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6785.315207 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 69062 99.92% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 44 0.06% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69116 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 67362 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24032.236276 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22252.228108 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15053.113927 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 66909 99.33% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 314 0.47% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 86 0.13% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 6 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 67362 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 372208258984 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.850822 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.356391 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 55541061216 14.92% 14.92% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 316652457768 85.07% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 13820000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 844000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 76000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 372208258984 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57010 98.45% 98.45% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 897 1.55% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 57907 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 82567 # Table walker walks requested +system.cpu1.itb.walker.walksLong 82567 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 985 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60088 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9957 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 72610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 937.467291 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 7808.036609 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 72461 99.79% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 121 0.17% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 72610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71030 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70173 98.79% 98.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 554 0.78% 99.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 204 0.29% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 25 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71030 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 397994478260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.871343 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.334985 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 51225264788 12.87% 12.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 346750110472 87.12% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 17741500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1276000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 85500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 397994478260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 60088 98.39% 98.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 985 1.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61073 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78571 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78571 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82567 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82567 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57907 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57907 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 136478 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 233650950 # ITB inst hits -system.cpu1.itb.inst_misses 78571 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61073 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61073 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 143640 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 204871540 # ITB inst hits +system.cpu1.itb.inst_misses 82567 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25813 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24862 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 177997 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205327 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 233729521 # ITB inst accesses -system.cpu1.itb.hits 233650950 # DTB hits -system.cpu1.itb.misses 78571 # DTB misses -system.cpu1.itb.accesses 233729521 # DTB accesses -system.cpu1.numPwrStateTransitions 26654 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 13327 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3530319846.850679 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 118121656427.394104 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3111 23.34% 23.34% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10193 76.48% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.95% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 7 0.05% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 204954107 # ITB inst accesses +system.cpu1.itb.hits 204871540 # DTB hits +system.cpu1.itb.misses 82567 # DTB misses +system.cpu1.itb.accesses 204954107 # DTB accesses +system.cpu1.numPwrStateTransitions 10338 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5169 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9100042413.076223 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 142913287882.442078 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3563 68.93% 68.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1580 30.57% 99.50% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.63% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.27% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7351151457424 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 13327 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 336351398021 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47048572598979 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 672713020 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7390880676264 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5169 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 346821221809 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 693644050 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 79728286 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 642468992 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 166724968 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 93734896 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 559167861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13053646 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1631240 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 271905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 4961771 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 667976 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 769069 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 233453036 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1554763 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 25728 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 653724931 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.120109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.251817 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 87527745 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 578391241 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 130931248 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 76096781 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 569305331 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14062296 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1768387 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 291884 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5735168 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 727906 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 800824 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 204645173 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1664411 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27214 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 673188393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.008077 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.227099 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 313299605 47.93% 47.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 112972876 17.28% 65.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 63087328 9.65% 74.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 164365122 25.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 348457754 51.76% 51.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 126514971 18.79% 70.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 42536092 6.32% 76.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 155679576 23.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 653724931 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.247840 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.955042 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 92976248 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 279392919 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 246557278 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 30153950 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4644536 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 16507277 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1918533 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 660010839 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21083339 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4644536 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 123063367 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 35472140 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 196207454 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 246305385 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 48032049 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 644623401 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5459169 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8046987 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 175179 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 243838 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19778119 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 13544 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 568046285 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 920205364 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 738028680 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 778046 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 516650091 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 51396188 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 12941129 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 11231119 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 61203121 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 135763785 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 72651809 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8023262 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7007249 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 625560135 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 13098005 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 628187829 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2397096 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 48439446 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31062607 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245074 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 653724931 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.960936 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.128164 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 673188393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.188759 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.833844 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 102787429 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 312284706 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 218180532 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34930241 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5005485 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18306368 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2064498 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 600925596 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22793962 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5005485 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 136395689 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44912882 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 210797905 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 219085305 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 56991127 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 584399745 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 6001663 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9489847 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 242679 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 273258 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 24369803 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10662 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 555653486 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 898470064 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 689649249 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 841085 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 500004101 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 55649379 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14907079 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13060204 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 70305418 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 96437745 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 82644936 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8695524 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7557089 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 562795340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15022202 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 566786483 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2618124 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 52408988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33720273 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 259964 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 673188393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.841943 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.073212 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 329147367 50.35% 50.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 114620484 17.53% 67.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 122782429 18.78% 86.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 80699819 12.34% 99.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6471130 0.99% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3702 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 363862102 54.05% 54.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 129787759 19.28% 73.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 109122281 16.21% 89.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 62914886 9.35% 98.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7497321 1.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4044 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 653724931 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 673188393 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 51549181 44.86% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 41748 0.04% 44.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 12676 0.01% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 10 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 30585339 26.62% 71.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 32314734 28.12% 99.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 48210 0.04% 99.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 356758 0.31% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 57388953 44.23% 44.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 51651 0.04% 44.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 16856 0.01% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 103 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 34250281 26.40% 70.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 37595364 28.98% 99.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 47943 0.04% 99.70% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 388183 0.30% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 418102293 66.56% 66.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1205881 0.19% 66.75% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 68687 0.01% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 9 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 15 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 25 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 73390 0.01% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 137792676 21.93% 88.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 70525871 11.23% 99.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 69235 0.01% 99.94% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 349710 0.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 385773007 68.06% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1187343 0.21% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69773 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 13 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 27 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 84205 0.01% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 2 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 98926523 17.45% 85.75% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 80304665 14.17% 99.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 64060 0.01% 99.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 376846 0.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 628187829 # Type of FU issued -system.cpu1.iq.rate 0.933813 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 114908656 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.182921 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2026010950 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 686704768 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 613194933 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1395389 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 519993 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 487253 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 742199086 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 897363 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2245530 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 566786483 # Type of FU issued +system.cpu1.iq.rate 0.817114 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 129739334 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228903 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1937625833 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 629808815 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 550243700 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1492982 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 556682 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 518492 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 695564416 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 961390 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2525668 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11142517 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 14462 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 128111 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 4846687 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12072145 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16264 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 139965 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5400546 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2292036 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3380084 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2506634 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3911021 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4644536 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5369264 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1350152 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 638773601 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5005485 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6180671 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1541266 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 577948873 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 135763785 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 72651809 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 10993874 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39251 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1271644 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 128111 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1722302 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2773233 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4495535 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 621090126 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 135058369 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6634352 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 96437745 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 82644936 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12856669 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62955 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1418771 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 139965 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1860771 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 3017279 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4878050 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 559031023 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 95939165 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7216233 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 115461 # number of nop insts executed -system.cpu1.iew.exec_refs 204845438 # number of memory reference insts executed -system.cpu1.iew.exec_branches 142702777 # Number of branches executed -system.cpu1.iew.exec_stores 69787069 # Number of stores executed -system.cpu1.iew.exec_rate 0.923262 # Inst execution rate -system.cpu1.iew.wb_sent 614366699 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 613682186 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 312164308 # num instructions producing a value -system.cpu1.iew.wb_consumers 462317181 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.912250 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.675217 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 42230538 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 12852931 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4178812 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 645679168 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.914105 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.588407 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 131331 # number of nop insts executed +system.cpu1.iew.exec_refs 175402489 # number of memory reference insts executed +system.cpu1.iew.exec_branches 104887487 # Number of branches executed +system.cpu1.iew.exec_stores 79463324 # Number of stores executed +system.cpu1.iew.exec_rate 0.805934 # Inst execution rate +system.cpu1.iew.wb_sent 551451357 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 550762192 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 266030186 # num instructions producing a value +system.cpu1.iew.wb_consumers 436524752 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.794013 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.609427 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 45696838 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14762238 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4541996 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 664504904 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.790677 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.583374 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 392186508 60.74% 60.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 104643933 16.21% 76.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 70768120 10.96% 87.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 40497706 6.27% 94.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10687024 1.66% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7435797 1.15% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5000033 0.77% 97.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3062259 0.47% 98.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 11397788 1.77% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 434201366 65.34% 65.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 119136384 17.93% 83.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 51278197 7.72% 90.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17339439 2.61% 93.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12299899 1.85% 95.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8244778 1.24% 96.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5665589 0.85% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3433584 0.52% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12905668 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 645679168 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 519872171 # Number of instructions committed -system.cpu1.commit.committedOps 590218687 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 664504904 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 446004136 # Number of instructions committed +system.cpu1.commit.committedOps 525408547 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 192426389 # Number of memory references committed -system.cpu1.commit.loads 124621267 # Number of loads committed -system.cpu1.commit.membars 28164164 # Number of memory barriers committed -system.cpu1.commit.branches 137852750 # Number of branches committed -system.cpu1.commit.fp_insts 479347 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 552778663 # Number of committed integer instructions. -system.cpu1.commit.function_calls 11814414 # Number of function calls committed. +system.cpu1.commit.refs 161609989 # Number of memory references committed +system.cpu1.commit.loads 84365599 # Number of loads committed +system.cpu1.commit.membars 3561329 # Number of memory barriers committed +system.cpu1.commit.branches 99629625 # Number of branches committed +system.cpu1.commit.fp_insts 509948 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 482210935 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12864051 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 396713394 67.21% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 957424 0.16% 67.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 54002 0.01% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 67436 0.01% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 124556243 21.10% 88.50% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 67458277 11.43% 99.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 65024 0.01% 99.94% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 346845 0.06% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 362699186 69.03% 69.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 966499 0.18% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55760 0.01% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 77071 0.01% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84306280 16.05% 85.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 76870874 14.63% 99.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 59319 0.01% 99.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 373516 0.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 590218687 # Class of committed instruction -system.cpu1.commit.bw_lim_events 11397788 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1262985389 # The number of ROB reads -system.cpu1.rob.rob_writes 1272910770 # The number of ROB writes -system.cpu1.timesIdled 874445 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18988089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94097134999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 519872171 # Number of Instructions Simulated -system.cpu1.committedOps 590218687 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.293997 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.293997 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.772799 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.772799 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 710414372 # number of integer regfile reads -system.cpu1.int_regfile_writes 423863042 # number of integer regfile writes -system.cpu1.fp_regfile_reads 765235 # number of floating regfile reads -system.cpu1.fp_regfile_writes 456552 # number of floating regfile writes -system.cpu1.cc_regfile_reads 104682480 # number of cc regfile reads -system.cpu1.cc_regfile_writes 105389899 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1284615439 # number of misc regfile reads -system.cpu1.misc_regfile_writes 12778028 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4692670 # number of replacements -system.cpu1.dcache.tags.tagsinuse 431.602875 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 183292694 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4693181 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.055109 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 431.602875 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.842974 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.842974 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 395805519 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 395805519 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 119760214 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 119760214 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 59584318 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 59584318 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168476 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 168476 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 151679 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 151679 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1458987 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1458987 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1477989 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1477989 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 179496211 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 179496211 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 179664687 # number of overall hits -system.cpu1.dcache.overall_hits::total 179664687 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5543636 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5543636 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 5953679 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 5953679 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 548675 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 548675 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445037 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 445037 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 238823 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 238823 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180840 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 180840 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 11942352 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 11942352 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 12491027 # number of overall misses -system.cpu1.dcache.overall_misses::total 12491027 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 78644271500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 78644271500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 105227667186 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 105227667186 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11004402882 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11004402882 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3255486500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3255486500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4308460000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4308460000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4407500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4407500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 194876341568 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 194876341568 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 194876341568 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 194876341568 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 125303850 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 125303850 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 65537997 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 65537997 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 717151 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 717151 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 596716 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 596716 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1697810 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1697810 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1658829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1658829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 191438563 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 191438563 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 192155714 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 192155714 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044242 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044242 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.090843 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.090843 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765076 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765076 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.745810 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.745810 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140665 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140665 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109017 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109017 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.062382 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.062382 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.065005 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.065005 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14186.406088 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14186.406088 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17674.393797 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17674.393797 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24726.939293 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24726.939293 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13631.377631 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13631.377631 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23824.706923 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23824.706923 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 525408547 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12905668 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1219098786 # The number of ROB reads +system.cpu1.rob.rob_writes 1150856845 # The number of ROB writes +system.cpu1.timesIdled 925679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 20455657 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94076236903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 446004136 # Number of Instructions Simulated +system.cpu1.committedOps 525408547 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.555241 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.555241 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.642987 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.642987 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 659945611 # number of integer regfile reads +system.cpu1.int_regfile_writes 391450025 # number of integer regfile writes +system.cpu1.fp_regfile_reads 826837 # number of floating regfile reads +system.cpu1.fp_regfile_writes 461620 # number of floating regfile writes +system.cpu1.cc_regfile_reads 120567774 # number of cc regfile reads +system.cpu1.cc_regfile_writes 121287073 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1215585693 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14957440 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5242137 # number of replacements +system.cpu1.dcache.tags.tagsinuse 459.717362 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 151071021 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5242649 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.815780 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8517875621500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.717362 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897885 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.897885 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 335085452 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 335085452 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 78683388 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78683388 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67788952 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67788952 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181257 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 181257 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 140156 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 140156 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1756750 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1756750 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1770273 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1770273 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 146612496 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 146612496 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 146793753 # number of overall hits +system.cpu1.dcache.overall_hits::total 146793753 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6126313 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6126313 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6911292 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6911292 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 643081 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 643081 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 451908 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 451908 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 241040 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 241040 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183733 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 183733 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13489513 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13489513 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14132594 # number of overall misses +system.cpu1.dcache.overall_misses::total 14132594 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 94548549000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 94548549000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 128933568944 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10455217570 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10455217570 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3390405500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3390405500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379858500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4379858500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2605000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2605000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 233937335514 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 233937335514 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84809701 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84809701 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 74700244 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 74700244 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824338 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 824338 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 592064 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 592064 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1997790 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1997790 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1954006 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1954006 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 160102009 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 160102009 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 160926347 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 160926347 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072236 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.072236 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.092520 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780118 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780118 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763276 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763276 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120653 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120653 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094029 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094029 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084256 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.084256 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087820 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087820 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16318.087222 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16318.087222 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15601.306567 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15601.306567 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2879860 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 16425129 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 370474 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 590630 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.773447 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 27.809507 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4692685 # number of writebacks -system.cpu1.dcache.writebacks::total 4692685 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2832127 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 2832127 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 4784793 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 4784793 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3576 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3576 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 7620496 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 7620496 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 7620496 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 7620496 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2711509 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2711509 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1168886 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1168886 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 548581 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 548581 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 441461 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 441461 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116569 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116569 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180840 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 180840 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4321856 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4321856 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4870437 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4870437 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22628 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22628 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21158 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43786 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43786 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35845036500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35845036500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21809849574 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21809849574 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12123846500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12123846500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10446547382 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10446547382 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1530530500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1530530500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4127725000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4127725000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4302500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4302500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68101433456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 68101433456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 80225279956 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 80225279956 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4008317000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4008317000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4008317000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4008317000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021639 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021639 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764945 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.764945 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739818 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739818 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068658 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068658 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109017 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109017 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.022576 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.022576 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025346 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.025346 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13219.589719 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13219.589719 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18658.662670 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18658.662670 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22100.376243 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22100.376243 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23663.579301 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23663.579301 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13129.824396 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13129.824396 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.287547 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.287547 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2644851 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 20463296 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 369952 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 688434 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.149173 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 29.724412 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5242162 # number of writebacks +system.cpu1.dcache.writebacks::total 5242162 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3113636 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3113636 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5578267 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5578267 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3659 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3659 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125068 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125068 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8695562 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8695562 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8695562 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8695562 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3012677 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3012677 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1333025 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1333025 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 643006 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 643006 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 448249 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 448249 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115972 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115972 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183726 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 183726 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4793951 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4793951 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5436957 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5436957 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8871 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17566 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42819104500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42819104500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26001782801 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26001782801 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14897861000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14897861000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9889085570 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9889085570 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1553813500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1553813500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4196193500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4196193500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2544000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2544000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78709972871 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 78709972871 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93607833871 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 93607833871 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354957000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1354957000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1354957000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1354957000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035523 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035523 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017845 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017845 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780027 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780027 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.757096 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.757096 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058050 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058050 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094025 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094025 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033785 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033785 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15757.450840 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15757.450840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16471.885368 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16471.885368 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177139.694184 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177139.694184 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91543.347189 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91543.347189 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5471432 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.529158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 227657285 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5471944 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 41.604462 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5955489 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.186843 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 198342876 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5956001 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.301350 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518419495000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.186843 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978881 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.978881 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 472364897 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 472364897 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 227657285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 227657285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 227657285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 227657285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 227657285 # number of overall hits -system.cpu1.icache.overall_hits::total 227657285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5789178 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5789178 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5789178 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5789178 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5789178 # number of overall misses -system.cpu1.icache.overall_misses::total 5789178 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62743690584 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 62743690584 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 62743690584 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 62743690584 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 62743690584 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 62743690584 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 233446463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 233446463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 233446463 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 233446463 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 233446463 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 233446463 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024799 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024799 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024799 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024799 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024799 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024799 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10838.100087 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10838.100087 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10838.100087 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10838.100087 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10838.100087 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10838.100087 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9340365 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 160 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 688454 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.567159 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5471432 # number of writebacks -system.cpu1.icache.writebacks::total 5471432 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 317207 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 317207 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 317207 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 317207 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 317207 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 317207 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5471971 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5471971 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5471971 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5471971 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5471971 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5471971 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 415232377 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 415232377 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 198342876 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 198342876 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 198342876 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 198342876 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 198342876 # number of overall hits +system.cpu1.icache.overall_hits::total 198342876 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6295293 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6295293 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6295293 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6295293 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6295293 # number of overall misses +system.cpu1.icache.overall_misses::total 6295293 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 67919445914 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 67919445914 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 67919445914 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 67919445914 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 67919445914 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 67919445914 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 204638169 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 204638169 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 204638169 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 204638169 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 204638169 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 204638169 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030763 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030763 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030763 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030763 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030763 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030763 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10788.925299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10788.925299 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9829448 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 701 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 729519 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.473875 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 233.666667 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 5955489 # number of writebacks +system.cpu1.icache.writebacks::total 5955489 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339254 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 339254 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 339254 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 339254 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 339254 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 339254 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956039 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5956039 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956039 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5956039 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956039 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5956039 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56670933881 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 56670933881 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56670933881 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 56670933881 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56670933881 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 56670933881 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023440 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023440 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023440 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10356.585201 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6370815 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6378826 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7261 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61337721519 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 61337721519 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61337721519 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 61337721519 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61337721519 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 61337721519 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6801498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6801498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6801498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6801498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029105 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.029105 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.029105 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10298.408308 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7017688 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7023313 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 5116 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 806238 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1756578 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12752.912837 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 9300002 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1772385 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.247168 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 831383 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2042934 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12933.505047 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10254699 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2058843 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.980807 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12466.059831 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 25.971588 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.261261 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 246.620158 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.760868 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001585 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000870 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015052 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.778376 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 338 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15390 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1774 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7283 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4523 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1607 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020630 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.939331 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 354225697 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 354225697 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 466688 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 176018 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 642706 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 2940618 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 2940618 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7221695 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7221695 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 24 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 733730 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 733730 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4959233 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4959233 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2549054 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2549054 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 189318 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 189318 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 466688 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 176018 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4959233 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3282784 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8884723 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 466688 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 176018 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4959233 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3282784 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8884723 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17962 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8568 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 26530 # number of ReadReq misses -system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208947 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 208947 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 180832 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 180832 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 231689 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 231689 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 512718 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 512718 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 826805 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 826805 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250101 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 250101 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17962 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8568 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 512718 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1058494 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1597742 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17962 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8568 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 512718 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1058494 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1597742 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 482745500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 237334000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 720079500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 968697500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 968697500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 281964000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 281964000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4142498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4142498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9580217985 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9580217985 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18416294000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18416294000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 27460876973 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 27460876973 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 376767000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 376767000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 482745500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 237334000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18416294000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 37041094958 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 56177468458 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 482745500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 237334000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18416294000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 37041094958 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 56177468458 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 484650 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184586 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 669236 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2940618 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 2940618 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 7221696 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 7221696 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208971 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 208971 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 180833 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 180833 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 965419 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 965419 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5471951 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5471951 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3375859 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3375859 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439419 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 439419 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 484650 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184586 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5471951 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4341278 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10482465 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 484650 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184586 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5471951 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4341278 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10482465 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046417 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.039642 # miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999885 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999885 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999994 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999994 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.418354 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 27.691890 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.361077 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.770510 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002223 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001690 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014976 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.789399 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 293 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15553 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 99 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1807 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7301 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1724 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017883 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.949280 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 390440087 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 390440087 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 557579 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186161 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 743740 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3343376 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3343376 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7851276 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7851276 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 859794 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 859794 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5412981 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 5412981 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2828036 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2828036 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191737 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 191737 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 557579 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186161 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5412981 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3687830 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9844551 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 557579 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186161 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5412981 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3687830 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9844551 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21615 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9433 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 31048 # number of ReadReq misses +system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses +system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224939 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 224939 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183720 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 183720 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255308 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 255308 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 543023 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 543023 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939708 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 939708 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256512 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 256512 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21615 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9433 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 543023 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1195016 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1769087 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21615 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9433 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 543023 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1195016 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1769087 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 686942500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 338389000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1025331500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939480500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 939480500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 264112000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 264112000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2448496 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2448496 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12203061000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 12203061000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19608835500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19608835500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34743736987 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34743736987 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 165000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 165000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 686942500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 338389000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19608835500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 46946797987 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 67580964987 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 686942500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 338389000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19608835500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 46946797987 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 67580964987 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 579194 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195594 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 774788 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3343377 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3343377 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 7851276 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 7851276 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224976 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 224976 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183720 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 183720 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115102 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1115102 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956004 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5956004 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3767744 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3767744 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448249 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 448249 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 579194 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195594 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5956004 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4882846 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11613638 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 579194 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195594 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5956004 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4882846 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11613638 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048227 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.040073 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999836 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999836 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.239988 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.239988 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093699 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093699 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244917 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244917 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.569163 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.569163 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046417 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093699 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243821 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.152420 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046417 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093699 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243821 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.152420 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 27700.046685 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27142.084433 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4636.091928 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4636.091928 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1559.259423 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1559.259423 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 591785.428571 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 591785.428571 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41349.472720 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41349.472720 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35918.953499 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35918.953499 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33213.244928 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33213.244928 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1506.459390 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1506.459390 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 27700.046685 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35918.953499 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34994.147306 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 35160.538096 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 27700.046685 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35918.953499 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34994.147306 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 35160.538096 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 270 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228955 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228955 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091172 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091172 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.249409 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.249409 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.572253 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.572253 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048227 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091172 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244738 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.152328 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048227 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091172 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244738 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.152328 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 35872.893035 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33024.075625 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4176.601212 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4176.601212 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1437.578924 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1437.578924 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 408082.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 408082.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47797.409404 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47797.409404 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36110.506369 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36110.506369 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36972.907528 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36972.907528 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.643245 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.643245 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 38201.040982 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 38201.040982 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 345 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 43.125000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 38780 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 938959 # number of writebacks -system.cpu1.l2cache.writebacks::total 938959 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 75 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 292 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6099 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 6099 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4092 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4092 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 9 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 9 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 75 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 292 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 10191 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 10561 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 75 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 292 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 10191 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 10561 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17887 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8276 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 26163 # number of ReadReq MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 611441 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 611441 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208947 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208947 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 180832 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 180832 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 225590 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 225590 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 512715 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 512715 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 822713 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 822713 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250092 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250092 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17887 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8276 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 512715 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1048303 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1587181 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17887 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8276 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 512715 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1048303 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 611441 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2198622 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 42412 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1137390 # number of writebacks +system.cpu1.l2cache.writebacks::total 1137390 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 59 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 256 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10963 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 10963 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3995 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3995 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 59 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 256 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14958 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 15274 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 59 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 256 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14958 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 15274 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21556 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9177 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 30733 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 745312 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 224939 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 224939 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183720 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183720 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244345 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 244345 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 543022 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 543022 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 935713 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 935713 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256509 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256509 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21556 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9177 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 543022 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1180058 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1753813 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21556 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9177 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 543022 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1180058 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2499125 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22628 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22695 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21158 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8938 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43786 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43853 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 182890500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 556885000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18622917019 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 18622917019 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3934960495 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3934960495 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2768973490 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2768973490 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3512498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3512498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7383230990 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7383230990 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15339884500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15339884500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22227595980 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22227595980 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6539695498 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6539695498 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 182890500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15339884500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 29610826970 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 45507596470 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 182890500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15339884500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 29610826970 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18622917019 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 64130513489 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6576000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3827109500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3833685500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6576000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3827109500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3833685500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039094 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17633 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 279014500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 835480000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36237678760 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4227924487 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4227924487 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2815609497 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2815609497 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2082496 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2082496 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9065423000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9065423000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16350690000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16350690000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28869020987 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28869020987 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5973751999 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5973751999 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 279014500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16350690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37934443987 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 55120613987 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 279014500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16350690000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37934443987 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 91358292747 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6298000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1283792500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1290090500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6298000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1283792500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1290090500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039666 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999885 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999885 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999994 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999994 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999836 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999836 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.233671 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.233671 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093699 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243705 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243705 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.569142 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.569142 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241473 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151413 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241473 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219123 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219123 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091172 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248348 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248348 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.572247 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.572247 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151013 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.209743 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21285.211941 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30457.422742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18832.337842 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18832.337842 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.408700 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15312.408700 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 501785.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 501785.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32728.538455 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32728.538455 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29918.930595 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27017.436190 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27017.436190 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26149.159101 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26149.159101 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28671.963985 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29168.503494 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169131.584762 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168922.031284 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87404.866852 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87421.282466 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 21096907 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10844448 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1776 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 550847 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 550845 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 772948 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9709968 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 21158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 21158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 3884973 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7223497 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1103932 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 773517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 20 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 412740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 326097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 449655 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 993079 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 971172 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5471971 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4312998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 499008 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 439419 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16415488 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15276269 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387820 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1031669 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33111246 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 700377584 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 584403341 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1476688 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3877200 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1290134813 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4431345 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 67169608 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15631904 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.053925 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.225870 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.215189 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23228623 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11943528 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 5072 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 598776 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 598706 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 70 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 867379 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10679013 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 8695 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 8695 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4499349 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7854270 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1254191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 938082 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 428069 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332128 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 468300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1145370 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1120388 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956039 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4785637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 521245 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 449809 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17867666 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16911297 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 409122 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1224107 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36412192 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762336624 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 654015560 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1564752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4633552 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1422550488 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5059056 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 80617704 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 17392868 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053991 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.226018 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14788958 94.61% 94.61% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 842944 5.39% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16453876 94.60% 94.60% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 938922 5.40% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 70 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15631904 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20975087949 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17392868 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23086793966 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 172744273 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 170580468 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8213479520 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8939751182 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 6968060036 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7774836803 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 203672612 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 213941664 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 547726569 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 645834647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution -system.iobus.trans_dist::WriteReq 136662 # Transaction distribution -system.iobus.trans_dist::WriteResp 136662 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40408 # Transaction distribution +system.iobus.trans_dist::ReadResp 40408 # Transaction distribution +system.iobus.trans_dist::WriteReq 136658 # Transaction distribution +system.iobus.trans_dist::WriteResp 136658 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47776 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3025,13 +3028,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122736 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122710 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231342 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354082 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3044,103 +3047,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155843 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155817 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339384 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497009 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37065503 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497287 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37041003 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24279001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24305002 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36411000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36394500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569676929 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570335330 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92805000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92783000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148038000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115614 # number of replacements -system.iocache.tags.tagsinuse 11.210449 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115667 # number of replacements +system.iocache.tags.tagsinuse 11.289924 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115683 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.838554 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.371895 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239910 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.460743 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.700653 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9156457442000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.417343 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.872581 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463584 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242036 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705620 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041054 # Number of tag accesses -system.iocache.tags.data_accesses 1041054 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041396 # Number of tag accesses +system.iocache.tags.data_accesses 1041396 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8943 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8980 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses -system.iocache.demand_misses::total 115673 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115671 # number of demand (read+write) misses +system.iocache.demand_misses::total 115711 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115633 # number of overall misses -system.iocache.overall_misses::total 115673 # number of overall misses +system.iocache.overall_misses::realview.ide 115671 # number of overall misses +system.iocache.overall_misses::total 115711 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1855240026 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1860440026 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13135197903 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13135197903 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14990437929 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14996006929 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14990437929 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14996006929 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1878808543 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1884008543 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 370000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 370000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13080956787 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13080956787 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5570000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14959765330 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14965335330 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5570000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14959765330 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14965335330 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8943 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8980 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115671 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115711 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115671 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115711 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3155,52 +3158,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 208336.892308 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 208056.366137 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123071.714105 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123071.714105 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129641.376371 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129641.376371 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 43392 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 209800.505902 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123333.333333 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139250 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129333.730847 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139250 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129333.730847 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 43850 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3516 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3467 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.341297 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.647822 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8943 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8980 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115671 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115711 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115671 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115711 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1409990026 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1413340026 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7789853273 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7789853273 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9199843299 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9203412299 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9199843299 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9203412299 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1431658543 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1435008543 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 220000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 220000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7738901569 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7738901569 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3570000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9170560112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9174130112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3570000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9170560112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9174130112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3215,663 +3218,655 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 158336.892308 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 158056.366137 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72987.906388 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72987.906388 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1186255 # number of replacements -system.l2c.tags.tagsinuse 65124.636684 # Cycle average of tags in use -system.l2c.tags.total_refs 6073175 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1247618 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.867816 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3083323500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12698.793405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 377.952725 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 459.111638 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5017.563285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 20561.842939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15825.160631 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.393148 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 11.333355 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4086.466074 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4153.822571 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1916.196912 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193768 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005767 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.313749 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.241473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.062355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.063382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993723 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11140 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49985 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 998 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 444 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2186 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4431 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43064 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.169983 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.762711 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 67662545 # Number of tag accesses -system.l2c.tags.data_accesses 67662545 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2448073 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2448073 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 187008 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 155703 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 342711 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 47244 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 46938 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 94182 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 49738 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49766 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 99504 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 10294 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4584 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 491338 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 542857 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 273502 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11332 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5195 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 468446 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 501967 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298805 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2608320 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 119780 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 141213 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 260993 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4584 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491338 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 592595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 273502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 11332 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 468446 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 551733 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 298805 # number of demand (read+write) hits -system.l2c.demand_hits::total 2707824 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4584 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491338 # number of overall hits -system.l2c.overall_hits::cpu0.data 592595 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 273502 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11332 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5195 # number of overall hits -system.l2c.overall_hits::cpu1.inst 468446 # number of overall hits -system.l2c.overall_hits::cpu1.data 551733 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 298805 # number of overall hits -system.l2c.overall_hits::total 2707824 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 26412 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 27413 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 53825 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 620 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 935 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1555 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77626 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 34061 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 111687 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1740 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1751 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 53308 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 132778 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 218721 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 625 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 445 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 44267 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 69080 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 92227 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 614942 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 449753 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 95020 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 544773 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1740 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 53308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 210404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 218721 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 625 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 445 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 44267 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 103141 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 92227 # number of demand (read+write) misses -system.l2c.demand_misses::total 726629 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1740 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1751 # number of overall misses -system.l2c.overall_misses::cpu0.inst 53308 # number of overall misses -system.l2c.overall_misses::cpu0.data 210404 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 218721 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 625 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 445 # number of overall misses -system.l2c.overall_misses::cpu1.inst 44267 # number of overall misses -system.l2c.overall_misses::cpu1.data 103141 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 92227 # number of overall misses -system.l2c.overall_misses::total 726629 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 156600500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 179260000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 335860500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7385500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7603500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 14989000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8419952993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3811911998 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12231864991 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181407500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 181058000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5842083500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15044752500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 72331000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 50453500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5031753500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 8306098000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 79765601293 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 31743500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 39384500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 71128000 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 181407500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 181058000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5842083500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23464705493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 72331000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 50453500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 5031753500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 12118009998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 91997466284 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 181407500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 181058000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5842083500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23464705493 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 72331000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 50453500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 5031753500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 12118009998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of overall miss cycles -system.l2c.overall_miss_latency::total 91997466284 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2448073 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2448073 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 213420 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 183116 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 396536 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 47864 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 47873 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 95737 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 127364 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 83827 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 211191 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 12034 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6335 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 544646 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 675635 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 492223 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 11957 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5640 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 512713 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 571047 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 391032 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3223262 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 569533 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 236233 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 805766 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 12034 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6335 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 544646 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 802999 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 492223 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 11957 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5640 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 512713 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 654874 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 391032 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3434453 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 12034 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6335 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 544646 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 802999 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 492223 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 11957 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5640 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 512713 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 654874 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 391032 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3434453 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.123756 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.149703 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.135738 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012953 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.019531 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.016242 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.609481 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.406325 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.528844 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276401 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097876 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.078901 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086339 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.120971 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.190783 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789687 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.402230 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.676093 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.276401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.097876 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.262023 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.078901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.086339 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.211571 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.276401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.097876 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.262023 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.078901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.086339 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.211571 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5929.142057 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6539.233211 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6239.860660 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11912.096774 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8132.085561 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9639.228296 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108468.206439 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111914.271395 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 109519.147179 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103402.627070 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109591.121408 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 113307.569778 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 113378.651685 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113668.274335 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 120238.824551 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 129712.397743 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 70.579852 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 414.486424 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 130.564474 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103402.627070 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 109591.121408 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 111522.145458 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 113378.651685 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 113668.274335 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 117489.747026 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 126608.580560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103402.627070 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 109591.121408 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 111522.145458 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 113378.651685 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 113668.274335 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 117489.747026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 126608.580560 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 2054 # number of cycles access was blocked +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1625787 # number of replacements +system.l2c.tags.tagsinuse 65181.204595 # Cycle average of tags in use +system.l2c.tags.total_refs 6817657 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1687923 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.039081 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3083223500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9617.868100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 445.484302 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 525.919749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4087.647415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 22210.879235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.752566 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 32.095436 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2691.005366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3224.848807 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1492.423894 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.146757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.008025 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.338911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.317738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000454 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.041061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994586 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12119 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49730 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1349 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 918 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9840 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4435 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42789 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.184921 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004379 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.758820 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 77430161 # Number of tag accesses +system.l2c.tags.data_accesses 77430161 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2884653 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2884653 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 199415 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 166641 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 366056 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 54285 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 48308 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 102593 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52113 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55927 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 108040 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12524 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4903 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 523305 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 612159 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 287889 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 14056 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5296 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 496370 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 569933 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304905 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2831340 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 116676 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 127973 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 244649 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 12524 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4903 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 523305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 664272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 287889 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 14056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 496370 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 625860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 304905 # number of demand (read+write) hits +system.l2c.demand_hits::total 2939380 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 12524 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4903 # number of overall hits +system.l2c.overall_hits::cpu0.inst 523305 # number of overall hits +system.l2c.overall_hits::cpu0.data 664272 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 287889 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 14056 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5296 # number of overall hits +system.l2c.overall_hits::cpu1.inst 496370 # number of overall hits +system.l2c.overall_hits::cpu1.data 625860 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 304905 # number of overall hits +system.l2c.overall_hits::total 2939380 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 23367 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 23265 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 46632 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 687 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 824 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1511 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 90180 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 49097 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139277 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3368 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 64819 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 175048 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1250 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 46649 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 114016 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 950404 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 450671 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 82488 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 533159 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3479 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3368 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 64819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 265228 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1814 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1250 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 46649 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 163113 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) misses +system.l2c.demand_misses::total 1089681 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3479 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3368 # number of overall misses +system.l2c.overall_misses::cpu0.inst 64819 # number of overall misses +system.l2c.overall_misses::cpu0.data 265228 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 338569 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1814 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1250 # number of overall misses +system.l2c.overall_misses::cpu1.inst 46649 # number of overall misses +system.l2c.overall_misses::cpu1.data 163113 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 201392 # number of overall misses +system.l2c.overall_misses::total 1089681 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 136803000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 150683000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 287486000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9622000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7084500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 16706500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9842771994 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5304657999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 15147429993 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 352314500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 351549500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7169242500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19597785998 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 196164500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 138775500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5424777500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 13175715998 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 128734883472 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 352314500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 351549500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 7169242500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 29440557992 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 196164500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 138775500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 5424777500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 18480373997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 143882313465 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 352314500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 351549500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 7169242500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 29440557992 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 196164500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 138775500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 5424777500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 18480373997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of overall miss cycles +system.l2c.overall_miss_latency::total 143882313465 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2884653 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2884653 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 222782 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 189906 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 412688 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 54972 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 49132 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 104104 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 142293 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 105024 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247317 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16003 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8271 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 588124 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 787207 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626458 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15870 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6546 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 543019 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 683949 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 506297 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3781744 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 567347 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 210461 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 777808 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 16003 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8271 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 588124 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 929500 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626458 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 15870 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 543019 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 788973 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 506297 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4029061 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 16003 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8271 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 588124 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 929500 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626458 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 15870 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 543019 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 788973 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 506297 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4029061 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.104887 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.122508 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.112996 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012497 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016771 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.014514 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.633763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.467484 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.563152 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.407206 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110213 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222366 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190956 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085907 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166702 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.251314 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.794348 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.391940 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.685464 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.407206 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.110213 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.285345 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.190956 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.085907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.206741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.270455 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.407206 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.110213 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.285345 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.190956 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.085907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.206741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.270455 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5854.538452 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6476.810660 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6164.993996 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14005.822416 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8597.694175 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 11056.585043 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 109145.841583 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108044.442614 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 108757.583758 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 104379.305226 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110604.028140 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111956.640453 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 111020.400000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 116289.255933 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115560.237142 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 135452.800569 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 132040.765568 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 132040.765568 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 7046 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 36 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 62 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 57.055556 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 113.645161 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 916327 # number of writebacks -system.l2c.writebacks::total 916327 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 108 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 101 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 252 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 108 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 101 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 108 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 101 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 252 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 42778 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 42778 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 26412 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 27413 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 53825 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 620 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 935 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1555 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 77626 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 34061 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 111687 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1739 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1751 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53200 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 132753 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 625 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 445 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44166 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 69063 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 614690 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 449753 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 95020 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 544773 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1739 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1751 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 53200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 210379 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 625 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 445 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 44166 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 103124 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 726377 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1739 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1751 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 53200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 210379 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 625 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 445 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 44166 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 103124 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 726377 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1244548 # number of writebacks +system.l2c.writebacks::total 1244548 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 102 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 118 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 19 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 254 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 102 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 118 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 102 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 118 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 254 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 67228 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 67228 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 23367 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 23265 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 46632 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 687 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 824 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1511 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 90180 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 49097 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139277 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3368 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64717 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 175033 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1250 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46531 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 113997 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 950150 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 450671 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 82488 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 533159 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3479 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3368 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 64717 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 265213 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1814 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1250 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 46531 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 163094 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1089427 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3479 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3368 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 64717 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 265213 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1814 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1250 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 46531 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 163094 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1089427 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22626 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 60008 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38561 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8869 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 59844 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38386 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 43784 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 98569 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 531562000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 578264000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1109826000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15032500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22996000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 38028500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7643531840 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3471120868 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11114652708 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163546503 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5300161563 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13714460643 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 46003500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4581236045 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7611577636 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 73592936232 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11245662562 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1996724000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 13242386562 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163546503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5300161563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21357992483 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 46003500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4581236045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 11082698504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 84707588940 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 163546503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5300161563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21357992483 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 46003500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4581236045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 11082698504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 84707588940 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17564 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 98230 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 466632500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483108499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 949740999 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16616499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20367500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 36983999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8940824795 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4813505389 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 13754330184 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 317869500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6512407062 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17845292687 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 126275001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4948966536 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12033347692 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 119208313229 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11145696799 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1615953000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 12761649799 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 317869500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 6512407062 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 26786117482 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 126275001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 4948966536 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 16846853081 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 132962643413 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 317869500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 6512407062 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 26786117482 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 126275001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 4948966536 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 16846853081 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 132962643413 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2535460001 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5368000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3419647503 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7444661004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4824158502 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5090000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1123983502 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7437417504 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2535460001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5368000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3419647503 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7444661004 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4824158502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5090000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1123983502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7437417504 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.123756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.149703 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.135738 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012953 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.019531 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.016242 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.609481 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406325 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196486 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.120941 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.190704 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789687 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.402230 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.676093 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.211497 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.211497 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20125.776162 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21094.517200 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20619.154668 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24245.967742 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24594.652406 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24455.627010 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98466.130420 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 101908.953583 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 99516.082516 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 103308.103342 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 110212.090931 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 119723.659458 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25004.085714 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21013.723427 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24308.081645 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.104887 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.122508 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.112996 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012497 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016771 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.014514 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.633763 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.467484 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.563152 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222347 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166675 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.251247 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.794348 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.391940 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.685464 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.270392 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.270392 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19969.722258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.463099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20366.722401 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24187.043668 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24717.839806 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24476.504964 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 99144.209304 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98040.723242 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98755.215750 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101953.875481 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158248.658158 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 151137.960886 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124061.141914 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75855.198235 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78102.674561 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 75527.407238 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3300545 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2017233 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4039865 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2364937 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3552 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 60008 # Transaction distribution -system.membus.trans_dist::ReadResp 683640 # Transaction distribution -system.membus.trans_dist::WriteReq 38561 # Transaction distribution -system.membus.trans_dist::WriteResp 38561 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1023021 # Transaction distribution -system.membus.trans_dist::CleanEvict 202426 # Transaction distribution -system.membus.trans_dist::UpgradeReq 359792 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 266371 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59844 # Transaction distribution +system.membus.trans_dist::ReadResp 1018974 # Transaction distribution +system.membus.trans_dist::WriteReq 38386 # Transaction distribution +system.membus.trans_dist::WriteResp 38386 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1351242 # Transaction distribution +system.membus.trans_dist::CleanEvict 267627 # Transaction distribution +system.membus.trans_dist::UpgradeReq 336754 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 267840 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 125029 # Transaction distribution -system.membus.trans_dist::ReadExResp 110917 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 623632 # Transaction distribution -system.membus.trans_dist::InvalidateReq 649188 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122736 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 152823 # Transaction distribution +system.membus.trans_dist::ReadExResp 138565 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 959130 # Transaction distribution +system.membus.trans_dist::InvalidateReq 652932 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30629 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122710 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3790913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3940187 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4178311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155843 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25810 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4892821 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5041417 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5279385 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155817 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 105399040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 105608363 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7265984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7265984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 112874347 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 584671 # Total snoops (count) -system.membus.snoopTraffic 181568 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2122585 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015284 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.122681 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 149644096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 149852089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7250176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157102265 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 616817 # Total snoops (count) +system.membus.snoopTraffic 199808 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2467715 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013862 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.116919 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2090143 98.47% 98.47% # Request fanout histogram -system.membus.snoop_fanout::1 32442 1.53% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2433507 98.61% 98.61% # Request fanout histogram +system.membus.snoop_fanout::1 34208 1.39% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2122585 # Request fanout histogram -system.membus.reqLayer0.occupancy 98177996 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2467715 # Request fanout histogram +system.membus.reqLayer0.occupancy 98169995 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22142995 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21686998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7123082230 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9247698101 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3974452270 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5871093052 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45639777 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 81490219 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3914,83 +3909,82 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10730258 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5842336 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1839840 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 143689 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 131126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 12563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 60010 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4055865 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38561 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38561 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3364400 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2413469 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 699420 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 360553 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1059973 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 190 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262551 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262551 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3996472 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 835150 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 805766 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8799068 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6846513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15645581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216011198 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 161148653 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 377159851 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2609772 # Total snoops (count) -system.toL2Bus.snoopTraffic 111390096 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7440116 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.386181 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.490329 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12086303 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6387551 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2235502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 239971 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 217052 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 22919 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59846 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4613854 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38386 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38386 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4129201 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2768870 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 702098 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 370433 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1072531 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298786 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4554900 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 905153 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 886862 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9925339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7679367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17604706 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 251196049 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 191962664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 443158713 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3147878 # Total snoops (count) +system.toL2Bus.snoopTraffic 132377296 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8556431 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.371457 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.488706 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4579449 61.55% 61.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2848104 38.28% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 12563 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5401002 63.12% 63.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3132510 36.61% 99.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 22919 0.27% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7440116 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8239335116 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8556431 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9443624545 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2574912 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 9237873 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4018530287 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4533014073 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3394272097 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3814018472 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5012 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13606 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13327 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5169 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 400af0c45..fa5414686 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.558690 # Number of seconds simulated -sim_ticks 51558690384000 # Number of ticks simulated -final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51558689626000 # Number of ticks simulated +final_tick 51558689626000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207581 # Simulator instruction rate (inst/s) -host_op_rate 243983 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9602431196 # Simulator tick rate (ticks/s) -host_mem_usage 695472 # Number of bytes of host memory used -host_seconds 5369.34 # Real time elapsed on the host -sim_insts 1114574366 # Number of instructions simulated -sim_ops 1310024478 # Number of ops (including micro ops) simulated +host_inst_rate 210245 # Simulator instruction rate (inst/s) +host_op_rate 247121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9737217389 # Simulator tick rate (ticks/s) +host_mem_usage 695392 # Number of bytes of host memory used +host_seconds 5295.01 # Real time elapsed on the host +sim_insts 1113248331 # Number of instructions simulated +sim_ops 1308509399 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory -system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 688064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 572736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6466080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114242184 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427328 # Number of bytes read from this memory +system.physmem.bytes_read::total 122396392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6466080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6466080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 142998784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 143019364 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 116985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1785047 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6677 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1928409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2234356 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 2236929 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 13345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 11108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 125412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2215770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2373924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 125412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 125412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2773515 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1896294 # Number of read requests accepted -system.physmem.writeReqs 2209882 # Number of write requests accepted -system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue -system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2773914 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2773515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 11108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 125412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2216169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5147838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1928410 # Number of read requests accepted +system.physmem.writeReqs 2236929 # Number of write requests accepted +system.physmem.readBursts 1928410 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2236929 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 123382976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35200 # Total number of bytes read from write queue +system.physmem.bytesWritten 143016896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 122396456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 143019364 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 550 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 112674 # Per bank write bursts -system.physmem.perBankRdBursts::1 120331 # Per bank write bursts -system.physmem.perBankRdBursts::2 120633 # Per bank write bursts -system.physmem.perBankRdBursts::3 114638 # Per bank write bursts -system.physmem.perBankRdBursts::4 113111 # Per bank write bursts -system.physmem.perBankRdBursts::5 123581 # Per bank write bursts -system.physmem.perBankRdBursts::6 115477 # Per bank write bursts -system.physmem.perBankRdBursts::7 120263 # Per bank write bursts -system.physmem.perBankRdBursts::8 112291 # Per bank write bursts -system.physmem.perBankRdBursts::9 145720 # Per bank write bursts -system.physmem.perBankRdBursts::10 114582 # Per bank write bursts -system.physmem.perBankRdBursts::11 120005 # Per bank write bursts -system.physmem.perBankRdBursts::12 112695 # Per bank write bursts -system.physmem.perBankRdBursts::13 118645 # Per bank write bursts -system.physmem.perBankRdBursts::14 113317 # Per bank write bursts -system.physmem.perBankRdBursts::15 117751 # Per bank write bursts -system.physmem.perBankWrBursts::0 133340 # Per bank write bursts -system.physmem.perBankWrBursts::1 139177 # Per bank write bursts -system.physmem.perBankWrBursts::2 138321 # Per bank write bursts -system.physmem.perBankWrBursts::3 137224 # Per bank write bursts -system.physmem.perBankWrBursts::4 136590 # Per bank write bursts -system.physmem.perBankWrBursts::5 143143 # Per bank write bursts -system.physmem.perBankWrBursts::6 136203 # Per bank write bursts -system.physmem.perBankWrBursts::7 139934 # Per bank write bursts -system.physmem.perBankWrBursts::8 134977 # Per bank write bursts -system.physmem.perBankWrBursts::9 143618 # Per bank write bursts -system.physmem.perBankWrBursts::10 135619 # Per bank write bursts -system.physmem.perBankWrBursts::11 140132 # Per bank write bursts -system.physmem.perBankWrBursts::12 134815 # Per bank write bursts -system.physmem.perBankWrBursts::13 138770 # Per bank write bursts -system.physmem.perBankWrBursts::14 136807 # Per bank write bursts -system.physmem.perBankWrBursts::15 138904 # Per bank write bursts +system.physmem.perBankRdBursts::0 114164 # Per bank write bursts +system.physmem.perBankRdBursts::1 120325 # Per bank write bursts +system.physmem.perBankRdBursts::2 121021 # Per bank write bursts +system.physmem.perBankRdBursts::3 117289 # Per bank write bursts +system.physmem.perBankRdBursts::4 115474 # Per bank write bursts +system.physmem.perBankRdBursts::5 125294 # Per bank write bursts +system.physmem.perBankRdBursts::6 117554 # Per bank write bursts +system.physmem.perBankRdBursts::7 120469 # Per bank write bursts +system.physmem.perBankRdBursts::8 115697 # Per bank write bursts +system.physmem.perBankRdBursts::9 146662 # Per bank write bursts +system.physmem.perBankRdBursts::10 119160 # Per bank write bursts +system.physmem.perBankRdBursts::11 123181 # Per bank write bursts +system.physmem.perBankRdBursts::12 118002 # Per bank write bursts +system.physmem.perBankRdBursts::13 121360 # Per bank write bursts +system.physmem.perBankRdBursts::14 114093 # Per bank write bursts +system.physmem.perBankRdBursts::15 118114 # Per bank write bursts +system.physmem.perBankWrBursts::0 133629 # Per bank write bursts +system.physmem.perBankWrBursts::1 139072 # Per bank write bursts +system.physmem.perBankWrBursts::2 140295 # Per bank write bursts +system.physmem.perBankWrBursts::3 139312 # Per bank write bursts +system.physmem.perBankWrBursts::4 138711 # Per bank write bursts +system.physmem.perBankWrBursts::5 145043 # Per bank write bursts +system.physmem.perBankWrBursts::6 137653 # Per bank write bursts +system.physmem.perBankWrBursts::7 140751 # Per bank write bursts +system.physmem.perBankWrBursts::8 137271 # Per bank write bursts +system.physmem.perBankWrBursts::9 144471 # Per bank write bursts +system.physmem.perBankWrBursts::10 139139 # Per bank write bursts +system.physmem.perBankWrBursts::11 142751 # Per bank write bursts +system.physmem.perBankWrBursts::12 139024 # Per bank write bursts +system.physmem.perBankWrBursts::13 141466 # Per bank write bursts +system.physmem.perBankWrBursts::14 137078 # Per bank write bursts +system.physmem.perBankWrBursts::15 138973 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 518 # Number of times write queue was full causing retry -system.physmem.totGap 51558689064500 # Total gap between requests +system.physmem.numWrRetry 512 # Number of times write queue was full causing retry +system.physmem.totGap 51558688241500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1875009 # Read request sizes (log2) +system.physmem.readPktSize::6 1907125 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2207309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2234356 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1137157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 697006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,167 +160,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 84750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 118181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 127464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 140930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 136900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 140021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 142369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 134210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 132730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 134518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 146577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 128734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 131799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2825 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::39 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 946985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.313381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.848752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.664857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 373897 39.48% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 237629 25.09% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90926 9.60% 74.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53224 5.62% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 39122 4.13% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 27360 2.89% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21677 2.29% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17745 1.87% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85405 9.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 946985 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 117910 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.350064 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 51.964300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 117905 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads -system.physmem.totQLat 70130172482 # Total ticks spent queuing -system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 117910 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 117910 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.952074 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.420057 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.842093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 113720 96.45% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1383 1.17% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 426 0.36% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 819 0.69% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 466 0.40% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 257 0.22% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 350 0.30% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 159 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 44 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 53 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 45 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 26 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 14 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 12 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 23 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 25 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 22 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 13 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 117910 # Writes before turning the bus around for reads +system.physmem.totQLat 71195410655 # Total ticks spent queuing +system.physmem.totMemAccLat 107342766905 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9639295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36929.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55679.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing -system.physmem.readRowHits 1529656 # Number of row buffer hits during reads -system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes -system.physmem.avgGap 12556375.83 # Average gap between requests -system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.490909 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states -system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states -system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states -system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.508949 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states -system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states -system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing +system.physmem.readRowHits 1556076 # Number of row buffer hits during reads +system.physmem.writeRowHits 1659436 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.26 # Row buffer hit rate for writes +system.physmem.avgGap 12378029.31 # Average gap between requests +system.physmem.pageHitRate 77.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3355628640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1783558920 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6794352600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5817512520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51361776960.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 51335807970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3128372160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 100703099850 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 75728818080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12253311191655 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12553360719255 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.477109 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51437874182990 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5229192000 # Time in different power states +system.physmem_0.memoryStateTime::REF 21823720000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51019823371500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 197210375905 # Time in different power states +system.physmem_0.memoryStateTime::ACT 93762531010 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 220840435585 # Time in different power states +system.physmem_1.actEnergy 3405851400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1810249155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6970560660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5847303060 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 52613798640.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 52063882650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3186128160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 104825729160 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 76862967360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12250174362465 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12557802494490 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.563259 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51436124881809 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5313449750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22355242000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51006079595250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 200164062707 # Time in different power states +system.physmem_1.memoryStateTime::ACT 94896006191 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 229881270102 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -337,30 +354,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 292068322 # Number of BP lookups -system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits +system.cpu.branchPred.lookups 291746368 # Number of BP lookups +system.cpu.branchPred.condPredicted 199670043 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13704274 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209695065 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131330914 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.629473 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37689025 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403296 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8150983 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6071547 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2079436 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 799941 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,91 +407,93 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1435892 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1432753 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1432753 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31582 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277767 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 672727 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 760026 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2835.541153 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 21869.031891 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 752912 99.06% 99.06% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4648 0.61% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 979 0.13% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 465 0.06% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 329 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.00% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 227 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 31 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 15 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 373 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 760026 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 802864 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26261.811465 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21447.525498 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20174.954942 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 783898 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 15255 1.90% 99.54% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1830 0.23% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 1111 0.14% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 417 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 138 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 67 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 44 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::589824-655359 88 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 802864 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1071344974520 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.740930 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520683 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1067157103520 99.61% 99.61% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2648963000 0.25% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 765456500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 299226500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 205947000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 124770000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 49360500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 91134000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2962000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 28500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1071344974520 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 277768 89.79% 89.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 31582 10.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 309350 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1432753 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1432753 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309350 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309350 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1742103 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 219013119 # DTB read hits -system.cpu.dtb.read_misses 1011306 # DTB read misses -system.cpu.dtb.write_hits 193770026 # DTB write hits -system.cpu.dtb.write_misses 424586 # DTB write misses +system.cpu.dtb.read_hits 218702786 # DTB read hits +system.cpu.dtb.read_misses 1008685 # DTB read misses +system.cpu.dtb.write_hits 193509885 # DTB write hits +system.cpu.dtb.write_misses 424068 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 88843 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 220024425 # DTB read accesses -system.cpu.dtb.write_accesses 194194612 # DTB write accesses +system.cpu.dtb.perms_faults 85947 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 219711471 # DTB read accesses +system.cpu.dtb.write_accesses 193933953 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 412783145 # DTB hits -system.cpu.dtb.misses 1435892 # DTB misses -system.cpu.dtb.accesses 414219037 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 412212671 # DTB hits +system.cpu.dtb.misses 1432753 # DTB misses +system.cpu.dtb.accesses 413645424 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,88 +523,92 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 178617 # Table walker walks requested -system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 178667 # Table walker walks requested +system.cpu.itb.walker.walksLong 178667 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1505 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 129431 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 20285 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 158382 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1812.216666 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 18363.278107 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 157121 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 1064 0.67% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 45 0.03% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-458751 4 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 38 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 58 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 158382 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151221 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29741.047870 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23638.717531 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 30785.807578 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 145088 95.94% 95.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5051 3.34% 99.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 405 0.27% 99.55% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 372 0.25% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 84 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 62 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 89 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 6 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 31 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 151221 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 912431133568 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.946195 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.225953 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 49158537652 5.39% 5.39% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 863207621416 94.61% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 64327000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 645500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 912431133568 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 129431 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1505 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130936 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178667 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 178667 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 465622680 # ITB inst hits -system.cpu.itb.inst_misses 178617 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130936 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130936 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309603 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 465155459 # ITB inst hits +system.cpu.itb.inst_misses 178667 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 62700 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 443616 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465801297 # ITB inst accesses -system.cpu.itb.hits 465622680 # DTB hits -system.cpu.itb.misses 178617 # DTB misses -system.cpu.itb.accesses 465801297 # DTB accesses -system.cpu.numPwrStateTransitions 34330 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 465334126 # ITB inst accesses +system.cpu.itb.hits 465155459 # DTB hits +system.cpu.itb.misses 178667 # DTB misses +system.cpu.itb.accesses 465334126 # DTB accesses +system.cpu.numPwrStateTransitions 34326 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17163 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2940291030.619589 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58535247231.170448 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7840 45.68% 45.68% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.11% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state @@ -598,110 +621,110 @@ system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2187140442 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 17163 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1094474667476 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50464214958524 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2188958665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed -system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 793327228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1301291266 # Number of instructions fetch has processed +system.cpu.fetch.Branches 291746368 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 175091486 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1303318637 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29494258 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4691335 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11697076 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1210879 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 464693718 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6899661 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52634 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2129020646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.716284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.134063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1402178691 65.86% 65.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 283295913 13.31% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 88951632 4.18% 83.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354594410 16.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2129020646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133281 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.594480 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 614901243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 887926164 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542267168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73189541 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10736530 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41417664 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4068147 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1415615504 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33076716 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10736530 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 677683388 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 94369025 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569420569 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 556850066 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219961068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1391316215 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8139294 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7433415 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 989914 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1107412 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 140152556 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22881 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1341380585 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2214711658 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1650667847 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1431319 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1262462841 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78917741 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44085987 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39608884 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160777326 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223759172 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 197950271 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12848262 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11112686 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1338031616 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44396038 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1368016868 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4222413 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73918251 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42115616 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 367601 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2129020646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.642557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.913774 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1277602195 60.01% 60.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 452152764 21.24% 81.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292326493 13.73% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96574735 4.54% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10335382 0.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29077 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2129020646 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73998347 33.81% 33.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90252 0.04% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26750 0.01% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 451 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available @@ -723,23 +746,23 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58933248 26.93% 60.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85092406 38.88% 99.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 64953 0.03% 99.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 641116 0.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945166591 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2943445 0.22% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129819 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 112220 0.01% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued @@ -761,98 +784,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 223636421 16.35% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 195247662 14.27% 99.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 119006 0.01% 99.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 661615 0.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued -system.cpu.iq.rate 0.626231 # Inst issue rate -system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1368016868 # Type of FU issued +system.cpu.iq.rate 0.624962 # Inst issue rate +system.cpu.iq.fu_busy_cnt 218847523 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.159974 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5085629992 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1455613237 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1345805572 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2494325 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 915085 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886623 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1585264941 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1599409 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5699315 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17397321 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21752 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184120 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8002822 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3610863 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2045833 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10736530 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13380632 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5317474 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1382714005 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 223759172 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 197950271 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39068255 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183844 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4942045 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184120 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4054774 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6111734 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10166508 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1354334153 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 218708027 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12279784 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 286874 # number of nop insts executed -system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed -system.cpu.iew.exec_branches 257488143 # Number of branches executed -system.cpu.iew.exec_stores 193779591 # Number of stores executed -system.cpu.iew.exec_rate 0.619964 # Inst execution rate -system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back -system.cpu.iew.wb_producers 576318139 # num instructions producing a value -system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value -system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle +system.cpu.iew.exec_nop 286351 # number of nop insts executed +system.cpu.iew.exec_refs 412227919 # number of memory reference insts executed +system.cpu.iew.exec_branches 257147927 # Number of branches executed +system.cpu.iew.exec_stores 193519892 # Number of stores executed +system.cpu.iew.exec_rate 0.618712 # Inst execution rate +system.cpu.iew.wb_sent 1347736728 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1346692195 # cumulative count of insts written-back +system.cpu.iew.wb_producers 575598964 # num instructions producing a value +system.cpu.iew.wb_consumers 947631330 # num instructions consuming a value +system.cpu.iew.wb_rate 0.615220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.607408 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 63004798 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44028437 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9693675 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2114795220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.618740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1434472892 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397205670 18.78% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150685224 7.13% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44578118 2.11% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36046556 1.70% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18010679 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11270632 0.53% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5868076 0.28% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16657373 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1114574366 # Number of instructions committed -system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2114795220 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1113248331 # Number of instructions committed +system.cpu.commit.committedOps 1308509399 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396823616 # Number of memory references committed -system.cpu.commit.loads 206620934 # Number of loads committed -system.cpu.commit.membars 9197183 # Number of memory barriers committed -system.cpu.commit.branches 249169048 # Number of branches committed -system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions. -system.cpu.commit.function_calls 31117535 # Number of function calls committed. +system.cpu.commit.refs 396309299 # Number of memory references committed +system.cpu.commit.loads 206361850 # Number of loads committed +system.cpu.commit.membars 9184659 # Number of memory barriers committed +system.cpu.commit.branches 248844974 # Number of branches committed +system.cpu.commit.fp_insts 874713 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1195788175 # Number of committed integer instructions. +system.cpu.commit.function_calls 31054705 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 909436322 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2554044 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103998 0.01% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction @@ -881,576 +904,575 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206248879 15.76% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 189291443 14.47% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 112971 0.01% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 656006 0.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction -system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3459813368 # The number of ROB reads -system.cpu.rob.rob_writes 2760364536 # The number of ROB writes -system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1114574366 # Number of Instructions Simulated -system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads -system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads -system.cpu.int_regfile_writes 949011498 # number of integer regfile writes -system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads -system.cpu.fp_regfile_writes 762248 # number of floating regfile writes -system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads -system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes -system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads -system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13773422 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1308509399 # Class of committed instruction +system.cpu.commit.bw_lim_events 16657373 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3460150362 # The number of ROB reads +system.cpu.rob.rob_writes 2757143126 # The number of ROB writes +system.cpu.timesIdled 9093879 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59938019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100928420629 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1113248331 # Number of Instructions Simulated +system.cpu.committedOps 1308509399 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.966281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.966281 # CPI: Total CPI of All Threads +system.cpu.ipc 0.508574 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.508574 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1608691208 # number of integer regfile reads +system.cpu.int_regfile_writes 947917634 # number of integer regfile writes +system.cpu.fp_regfile_reads 1422673 # number of floating regfile reads +system.cpu.fp_regfile_writes 763952 # number of floating regfile writes +system.cpu.cc_regfile_reads 314581614 # number of cc regfile reads +system.cpu.cc_regfile_writes 315450766 # number of cc regfile writes +system.cpu.misc_regfile_reads 3476012517 # number of misc regfile reads +system.cpu.misc_regfile_writes 44950556 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13775006 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982219 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363107662 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13775518 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.358912 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982219 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits -system.cpu.dcache.overall_hits::total 353374705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18866989 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2064832 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2064832 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1271634 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1271634 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 551153 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 551153 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1608531103 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1608531103 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 187963659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 187963659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164128124 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164128124 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464529 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464529 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334911 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334911 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4841304 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4841304 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5331661 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5331661 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 352426694 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 352426694 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 352891223 # number of overall hits +system.cpu.dcache.overall_hits::total 352891223 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12866276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12866276 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18869425 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18869425 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2066021 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2066021 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270837 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270837 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 552138 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 552138 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 33012979 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 33012979 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 35077811 # number of overall misses -system.cpu.dcache.overall_misses::total 35077811 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 223063102000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 223063102000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1108624638487 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1108624638487 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30055916196 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 30055916196 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9351183000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 9351183000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1361743656683 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1361743656683 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1361743656683 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1361743656683 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201068174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201068174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 183248827 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 183248827 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2529776 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2529776 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605739 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1605739 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5397312 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5397312 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335622 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5335622 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385922740 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385922740 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 388452516 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 388452516 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064030 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064030 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102958 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.102958 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816211 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816211 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791931 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791931 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102116 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102116 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085543 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085543 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17326.156120 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17326.156120 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58760.019338 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58760.019338 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23635.665762 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23635.665762 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16966.582782 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16966.582782 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35687.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35687.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41248.736041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41248.736041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38820.656645 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38820.656645 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28867036 # number of cycles access was blocked +system.cpu.dcache.demand_misses::cpu.data 33006538 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 33006538 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 35072559 # number of overall misses +system.cpu.dcache.overall_misses::total 35072559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 225016613000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 225016613000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113555465610 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1113555465610 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30066239407 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 30066239407 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9389478000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 9389478000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 268500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 268500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1368638318017 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1368638318017 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1368638318017 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1368638318017 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 200829935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 200829935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 182997549 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 182997549 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2530550 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2530550 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605748 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1605748 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5393442 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5393442 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5331669 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5331669 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 385433232 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385433232 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 387963782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 387963782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064066 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103113 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.103113 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816432 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.816432 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791430 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791430 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.085635 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085635 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090402 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17488.868807 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17488.868807 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59013.746609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59013.746609 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23658.611928 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23658.611928 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17005.672495 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17005.672495 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33562.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33562.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41465.673195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41465.673195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39023.052695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39023.052695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29226576 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2109714 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2109542 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.682914 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.854465 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10417036 # number of writebacks -system.cpu.dcache.writebacks::total 10417036 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5763320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5763320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15767233 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15767233 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7067 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7067 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 267203 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 267203 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21537620 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21537620 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21537620 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21537620 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111036 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7111036 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099756 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3099756 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2058030 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2058030 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1264567 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1264567 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283950 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 10412623 # number of writebacks +system.cpu.dcache.writebacks::total 10412623 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5753869 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5753869 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15770096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15770096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6914 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6914 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 268040 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 268040 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21530879 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21530879 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21530879 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21530879 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7112407 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7112407 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099329 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3099329 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2059217 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2059217 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263923 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263923 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284098 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 284098 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11475359 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11475359 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13533389 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13533389 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11475659 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11475659 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13534876 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13534876 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 117823858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 117823858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163535842014 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 163535842014 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34754745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34754745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28487682196 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28487682196 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4220692000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4220692000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 309847382210 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 309847382210 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 344602127210 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 344602127210 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225657500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225657500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225657500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225657500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035366 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16948036 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 119879387000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 119879387000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164321917838 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 164321917838 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34890815500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34890815500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28496186907 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28496186907 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4243086000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4243086000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 260500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 260500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312697491745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 312697491745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 347588307245 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 347588307245 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225622500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225622500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035415 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035415 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016936 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016936 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813743 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813743 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787124 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787124 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052675 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052675 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029773 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029773 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034887 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034887 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16854.967242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16854.967242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53018.546220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53018.546220 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16943.729340 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16943.729340 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22545.825107 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22545.825107 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14935.289935 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14935.289935 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27248.761204 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27248.761204 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25680.937693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25680.937693 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184780.437493 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184780.437493 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.139105 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.139105 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16945634 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953469 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 446936468 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16946146 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.373930 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13767479500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953469 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses -system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 447400638 # number of overall hits -system.cpu.icache.overall_hits::total 447400638 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17740135 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17740135 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17740135 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17740135 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17740135 # number of overall misses -system.cpu.icache.overall_misses::total 17740135 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 237745686369 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 237745686369 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 237745686369 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 237745686369 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 237745686369 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 237745686369 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465140773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465140773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465140773 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465140773 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465140773 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465140773 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038139 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038139 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038139 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038139 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 481618789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 481618789 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 446936468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 446936468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 446936468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 446936468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 446936468 # number of overall hits +system.cpu.icache.overall_hits::total 446936468 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17735952 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17735952 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17735952 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17735952 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17735952 # number of overall misses +system.cpu.icache.overall_misses::total 17735952 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 237635395867 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 237635395867 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 237635395867 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 237635395867 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 237635395867 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 237635395867 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 464672420 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 464672420 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 464672420 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 464672420 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 464672420 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 464672420 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038169 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038169 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038169 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038169 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038169 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038169 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13398.513701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13398.513701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13398.513701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13398.513701 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21075 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1467 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.366053 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16948036 # number of writebacks -system.cpu.icache.writebacks::total 16948036 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791363 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 791363 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 791363 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 791363 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 16945634 # number of writebacks +system.cpu.icache.writebacks::total 16945634 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789581 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 789581 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 789581 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 789581 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 789581 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 789581 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16946371 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16946371 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16946371 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16946371 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16946371 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16946371 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213645244880 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 213645244880 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213645244880 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 213645244880 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213645244880 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 213645244880 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213535123378 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 213535123378 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213535123378 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 213535123378 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213535123378 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 213535123378 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036438 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036438 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036438 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12605.352463 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12605.352463 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036470 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036470 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036470 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12600.640183 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12600.640183 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2368264 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65438.912903 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 59342443 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2431405 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.406647 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9464.122529 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 393.883765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.035779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6680.528058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48467.342772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.144411 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006010 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101937 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.739553 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998519 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62889 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1615511 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 10417036 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 10417036 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 16945412 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16945412 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39342 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39342 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1735264 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1735264 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16852583 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16852583 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 9020162 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 9020162 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 672287 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 672287 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 1306072 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 309439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 16852583 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10755426 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 29223520 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 1306072 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 309439 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 16852583 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10755426 # number of overall hits -system.cpu.l2cache.overall_hits::total 29223520 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10647 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 19606 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4043 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4043 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1337553 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1337553 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95970 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 95970 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 416410 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 416410 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 592280 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 592280 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 10647 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 8959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 95970 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1753963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1869539 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 10647 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 8959 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 95970 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1753963 # number of overall misses -system.cpu.l2cache.overall_misses::total 1869539 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1464838500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 979350000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2444188500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73726500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 73726500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 139978365500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 139978365500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10559308500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 10559308500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46880784000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 46880784000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 453500 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 453500 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1464838500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 979350000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10559308500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 186859149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 199862646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1464838500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 979350000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10559308500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 186859149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 199862646500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1316719 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 318398 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1635117 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 10417036 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 10417036 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 16945412 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16945412 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43385 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43385 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2400192 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65402.662910 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 59310777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2462586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.084754 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2677803000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9273.019739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 380.440424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.878818 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6709.693607 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48618.630322 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.141495 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005805 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006422 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.102382 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.741861 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 239 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 998 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5581 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55200 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003647 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948410 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 508162919 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 508162919 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1310607 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 311860 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1622467 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 10412623 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 10412623 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 16942916 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 16942916 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39365 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39365 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1729760 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1729760 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16850415 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16850415 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8995594 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 8995594 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 670573 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 670573 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 1310607 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 311860 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 16850415 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10725354 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 29198236 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 1310607 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 311860 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 16850415 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10725354 # number of overall hits +system.cpu.l2cache.overall_hits::total 29198236 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10751 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8953 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 19704 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4081 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4081 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1342610 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1342610 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95730 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 95730 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 443644 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 443644 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 593350 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 593350 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 10751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 8953 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 95730 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1786254 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1901688 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 10751 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 8953 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 95730 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1786254 # number of overall misses +system.cpu.l2cache.overall_misses::total 1901688 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1481609000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 989051000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2470660000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73641000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 73641000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140820985000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 140820985000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10474446000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 10474446000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49360603500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49360603500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1481609000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 989051000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10474446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 190181588500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 203126694500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1481609000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 989051000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10474446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 190181588500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 203126694500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1321358 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 320813 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1642171 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 10412623 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 10412623 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 16942916 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 16942916 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43446 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 43446 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072817 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3072817 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16948553 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 16948553 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9436572 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 9436572 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1264567 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1264567 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1316719 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 318398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 16948553 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 12509389 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 31093059 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1316719 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 318398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16948553 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 12509389 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 31093059 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008086 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028138 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093189 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093189 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435286 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.435286 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.468366 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.468366 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008086 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028138 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.140212 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060127 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008086 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028138 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.140212 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137582.276698 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109314.655654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 124665.332041 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18235.592382 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18235.592382 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104652.574889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104652.574889 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110027.180369 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110027.180369 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112583.232871 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112583.232871 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.765685 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.765685 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 106904.775188 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 106904.775188 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3072370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16946145 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 16946145 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439238 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 9439238 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263923 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1263923 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1321358 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 320813 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 16946145 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 12511608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 31099924 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1321358 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 320813 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16946145 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 12511608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 31099924 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027907 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.011999 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093933 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093933 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.375000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.375000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436995 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436995 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005649 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005649 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047000 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047000 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.469451 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.469451 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008136 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027907 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005649 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.142768 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061148 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008136 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027907 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005649 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.142768 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061148 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137811.273370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 110471.462080 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 125388.753553 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18044.841951 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18044.841951 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104885.994444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104885.994444 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109416.546537 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109416.546537 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111261.740269 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111261.740269 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 106813.890870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 106813.890870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 2100679 # number of writebacks -system.cpu.l2cache.writebacks::total 2100679 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2127726 # number of writebacks +system.cpu.l2cache.writebacks::total 2127726 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10647 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 19606 # number of ReadReq MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4043 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4043 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1337553 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1337553 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95970 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95970 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 416389 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 416389 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 592280 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 592280 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 95970 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753942 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1869518 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10647 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 95970 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753942 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1869518 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8949 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 19700 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4081 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4081 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1342610 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1342610 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95730 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95730 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 443623 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 443623 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 593350 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 593350 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 95730 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1786233 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1901663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8949 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 95730 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1786233 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1901663 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable @@ -1459,156 +1481,156 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 889760000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2248128500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77144500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77144500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126602809555 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126602809555 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9599588543 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9599588543 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42714761570 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42714761570 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12256085002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12256085002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 889760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9599588543 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169317571125 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 181165288168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 889760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9599588543 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169317571125 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 181165288168 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 899358000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2273457000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77835000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77835000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127394865041 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127394865041 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9517134048 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9517134048 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 44922827064 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 44922827064 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12274426752 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12274426752 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 899358000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9517134048 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172317692105 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 184108283153 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 899358000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9517134048 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172317692105 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 184108283153 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804371500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290859000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804330500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290818000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804330500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290818000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011996 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093933 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093933 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.375000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005649 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.046998 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.046998 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.469451 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.469451 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061147 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061147 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115403.908629 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19072.531242 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19072.531242 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94885.979578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94885.979578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99416.421686 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99416.421686 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101263.521197 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101263.521197 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.655013 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.655013 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172276.222842 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.078493 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.052229 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82206.564512 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62406736 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31684635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4771 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2157 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2157 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2262463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28648866 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12540349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16945634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3634849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43449 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2976479 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3072370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3072370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16946371 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1296845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263929 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41548571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 789343 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3060305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 96278955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169414432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467392114 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2566504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10570864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3649943914 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3001846 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 140762320 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35497041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026133 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159532 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34569387 97.39% 97.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 927654 2.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35497041 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 59266206483 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1503389 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25451406259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19476952327 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 468902194 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1739672503 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40306 # Transaction distribution +system.iobus.trans_dist::ReadResp 40306 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1625,11 +1647,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1644,16 +1666,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41898000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 340000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1671,75 +1693,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25176500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36502500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568938305 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115456 # number of replacements -system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115466 # number of replacements +system.iocache.tags.tagsinuse 10.450358 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13091904723000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528286 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922072 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432629 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039632 # Number of tag accesses -system.iocache.tags.data_accesses 1039632 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039722 # Number of tag accesses +system.iocache.tags.data_accesses 1039722 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses -system.iocache.demand_misses::total 115515 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses +system.iocache.demand_misses::total 115525 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115475 # number of overall misses -system.iocache.overall_misses::total 115515 # number of overall misses +system.iocache.overall_misses::realview.ide 115485 # number of overall misses +system.iocache.overall_misses::total 115525 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1915316073 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1920401573 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13385817732 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13385817732 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15301133805 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15306570305 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15301133805 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15306570305 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1754,52 +1776,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217131.399274 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 216798.551930 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125495.178617 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125495.178617 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132495.739494 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132495.739494 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 46527 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.537096 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1474266073 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1477501573 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8047307820 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8047307820 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9521573893 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9525010393 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9521573893 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9525010393 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1814,94 +1836,95 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167131.399274 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166798.551930 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75445.396947 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75445.396947 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5129530 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2552281 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3338 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 595799 # Transaction distribution +system.membus.trans_dist::ReadResp 622896 # Transaction distribution system.membus.trans_dist::WriteReq 33703 # Transaction distribution system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution -system.membus.trans_dist::CleanEvict 275154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2234356 # Transaction distribution +system.membus.trans_dist::CleanEvict 280040 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4640 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution -system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution -system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution +system.membus.trans_dist::ReadExReq 1342054 # Transaction distribution +system.membus.trans_dist::ReadExResp 1342054 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 567911 # Transaction distribution +system.membus.trans_dist::InvalidateReq 700014 # Transaction distribution +system.membus.trans_dist::InvalidateResp 32639 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6846190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6975852 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7213520 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2809 # Total snoops (count) -system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2670049 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258164108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 258334162 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7251648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 265585810 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 35487 # Total snoops (count) +system.membus.snoopTraffic 181760 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2703311 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013318 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.114632 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram -system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2667309 98.67% 98.67% # Request fanout histogram +system.membus.snoop_fanout::1 36002 1.33% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2670049 # Request fanout histogram -system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2703311 # Request fanout histogram +system.membus.reqLayer0.occupancy 104009500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5608500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14476553313 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10180600996 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 79038203 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1944,30 +1967,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17163 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index e4db2f557..af7693171 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.296282 # Number of seconds simulated -sim_ticks 47296281748500 # Number of ticks simulated -final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.177074 # Number of seconds simulated +sim_ticks 47177073828000 # Number of ticks simulated +final_tick 47177073828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1698090 # Simulator instruction rate (inst/s) -host_op_rate 1997558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82199406118 # Simulator tick rate (ticks/s) -host_mem_usage 696116 # Number of bytes of host memory used -host_seconds 575.38 # Real time elapsed on the host -sim_insts 977055082 # Number of instructions simulated -sim_ops 1149364510 # Number of ops (including micro ops) simulated +host_inst_rate 1523218 # Simulator instruction rate (inst/s) +host_op_rate 1791835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73539001789 # Simulator tick rate (ticks/s) +host_mem_usage 696552 # Number of bytes of host memory used +host_seconds 641.52 # Real time elapsed on the host +sim_insts 977181439 # Number of instructions simulated +sim_ops 1149505972 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 154816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4238644 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35981768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 224128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3009416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 39414640 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402560 # Number of bytes read from this memory -system.physmem.bytes_read::total 83777076 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4238644 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3009416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7248060 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 102370496 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 157952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4192628 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35968392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3097544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 39307632 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory +system.physmem.bytes_read::total 83713716 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4192628 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3097544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7290172 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 102127744 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 102391080 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 106636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 562228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 615870 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1349560 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1599539 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 102148328 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 105917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 562019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 614198 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1348570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1595746 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1602113 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 89619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 760774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 833356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1771325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 89619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63629 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 153248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2164451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1598320 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 88870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 762413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 833194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1774458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 88870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2164775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2164886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2164451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 89619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 761209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 833356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3936211 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2165211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2164775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 88870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 762849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 833194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3939669 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -100,9 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -110,7 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -140,47 +140,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 125159 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 123270 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123270 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123270 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123270 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123270 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 94962 90.03% 90.03% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10516 9.97% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 105478 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123270 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123270 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105478 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105478 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 228748 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 92471463 # DTB read hits -system.cpu0.dtb.read_misses 88826 # DTB read misses -system.cpu0.dtb.write_hits 85455153 # DTB write hits -system.cpu0.dtb.write_misses 36333 # DTB write misses +system.cpu0.dtb.read_hits 90958252 # DTB read hits +system.cpu0.dtb.read_misses 87293 # DTB read misses +system.cpu0.dtb.write_hits 84301704 # DTB write hits +system.cpu0.dtb.write_misses 35977 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 35878 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5554 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92560289 # DTB read accesses -system.cpu0.dtb.write_accesses 85491486 # DTB write accesses +system.cpu0.dtb.perms_faults 10284 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91045545 # DTB read accesses +system.cpu0.dtb.write_accesses 84337681 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 177926616 # DTB hits -system.cpu0.dtb.misses 125159 # DTB misses -system.cpu0.dtb.accesses 178051775 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 175259956 # DTB hits +system.cpu0.dtb.misses 123270 # DTB misses +system.cpu0.dtb.accesses 175383226 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -210,467 +210,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 61082 # Table walker walks requested -system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 60279 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60279 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60279 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60279 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60279 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54211 98.84% 98.84% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 635 1.16% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54846 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60279 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60279 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 496679820 # ITB inst hits -system.cpu0.itb.inst_misses 61082 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54846 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54846 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115125 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 489463139 # ITB inst hits +system.cpu0.itb.inst_misses 60279 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 24716 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses -system.cpu0.itb.hits 496679820 # DTB hits -system.cpu0.itb.misses 61082 # DTB misses -system.cpu0.itb.accesses 496740902 # DTB accesses -system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 489523418 # ITB inst accesses +system.cpu0.itb.hits 489463139 # DTB hits +system.cpu0.itb.misses 60279 # DTB misses +system.cpu0.itb.accesses 489523418 # DTB accesses +system.cpu0.numPwrStateTransitions 26258 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13129 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3571424062.507959 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 90351330790.457672 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3131 23.85% 23.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9971 75.95% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94592576721 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7510114609000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13129 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 287847311333 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46889226516667 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94354160786 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed -system.cpu0.committedInsts 496443686 # Number of instructions committed -system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses -system.cpu0.num_func_calls 28899937 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls -system.cpu0.num_int_insts 535025290 # number of integer instructions -system.cpu0.num_fp_insts 524584 # number of float instructions -system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read -system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written -system.cpu0.num_mem_refs 178027643 # number of memory refs -system.cpu0.num_load_insts 92545018 # Number of load instructions -system.cpu0.num_store_insts 85482625 # Number of store instructions -system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles -system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles -system.cpu0.Branches 111093071 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13129 # number of quiesce instructions executed +system.cpu0.committedInsts 489228722 # Number of instructions committed +system.cpu0.committedOps 575357792 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 527304848 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 518985 # Number of float alu accesses +system.cpu0.num_func_calls 28507888 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 75158499 # number of instructions that are conditional controls +system.cpu0.num_int_insts 527304848 # number of integer instructions +system.cpu0.num_fp_insts 518985 # number of float instructions +system.cpu0.num_int_register_reads 772493030 # number of times the integer registers were read +system.cpu0.num_int_register_writes 418386904 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 837696 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 439396 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 131494560 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 131170441 # number of times the CC registers were written +system.cpu0.num_mem_refs 175360180 # number of memory refs +system.cpu0.num_load_insts 91031152 # Number of load instructions +system.cpu0.num_store_insts 84329028 # Number of store instructions +system.cpu0.num_idle_cycles 93778466083.220322 # Number of idle cycles +system.cpu0.num_busy_cycles 575694702.779680 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006101 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993899 # Percentage of idle cycles +system.cpu0.Branches 109461640 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction -system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction -system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 8 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 13 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 21 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMisc 72938 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 92483705 15.83% 85.35% # Class of executed instruction -system.cpu0.op_class::MemWrite 85092334 14.57% 99.92% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 61313 0.01% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 390291 0.07% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 398983706 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 1214289 0.21% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 59472 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 8 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 13 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 21 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMisc 72490 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 90970869 15.80% 85.34% # Class of executed instruction +system.cpu0.op_class::MemWrite 83942858 14.58% 99.92% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 60283 0.01% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 386170 0.07% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 584096590 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6248914 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 171607957 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6249426 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.459795 # Average number of references to valid blocks. +system.cpu0.op_class::total 575690180 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6169123 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.902441 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169021316 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6169635 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.395675 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.902441 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982231 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.982231 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 362271539 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 362271539 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80674063 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80674063 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261006 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 261006 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087975 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2087975 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051823 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2051823 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 166959241 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 166959241 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167175510 # number of overall hits -system.cpu0.dcache.overall_hits::total 167175510 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1477781 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1477781 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824193 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 824193 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119751 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 119751 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154814 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 154814 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5600396 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5600396 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6369959 # number of overall misses -system.cpu0.dcache.overall_misses::total 6369959 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017988 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017988 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759486 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759486 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054242 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054242 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032455 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032455 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036705 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036705 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 356856913 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 356856913 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 84588460 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 84588460 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79569773 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79569773 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213774 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 213774 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259782 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259782 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2069774 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2069774 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2033350 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2033350 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164418015 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164418015 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164631789 # number of overall hits +system.cpu0.dcache.overall_hits::total 164631789 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3250756 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3250756 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1461940 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1461940 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 763460 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 763460 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 814949 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 814949 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 115689 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 115689 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 151036 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 151036 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5527645 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5527645 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6291105 # number of overall misses +system.cpu0.dcache.overall_misses::total 6291105 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87839216 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87839216 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81031713 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81031713 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 977234 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 977234 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1074731 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1074731 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2185463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184386 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2184386 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169945660 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 169945660 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170922894 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 170922894 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018042 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018042 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781246 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781246 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758282 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758282 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052936 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052936 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.069143 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069143 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032526 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032526 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036807 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036807 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6248914 # number of writebacks -system.cpu0.dcache.writebacks::total 6248914 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5509624 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 491225330 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5510136 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.149402 # Average number of references to valid blocks. +system.cpu0.dcache.writebacks::writebacks 6169123 # number of writebacks +system.cpu0.dcache.writebacks::total 6169123 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5445857 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 484071611 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5446369 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.879694 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 998981083 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 998981083 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 491225330 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 491225330 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 491225330 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 491225330 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 491225330 # number of overall hits -system.cpu0.icache.overall_hits::total 491225330 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5510141 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5510141 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5510141 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5510141 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5510141 # number of overall misses -system.cpu0.icache.overall_misses::total 5510141 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 984482344 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 984482344 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 484071611 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 484071611 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 484071611 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 484071611 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 484071611 # number of overall hits +system.cpu0.icache.overall_hits::total 484071611 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5446374 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5446374 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5446374 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5446374 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5446374 # number of overall misses +system.cpu0.icache.overall_misses::total 5446374 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 489517985 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 489517985 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 489517985 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 489517985 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 489517985 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 489517985 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011126 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011126 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011126 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011126 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011126 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011126 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5509624 # number of writebacks -system.cpu0.icache.writebacks::total 5509624 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 5445857 # number of writebacks +system.cpu0.icache.writebacks::total 5445857 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2567589 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15706.944975 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9429067 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2583246 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.650085 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2533357 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15711.685213 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9303903 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2548994 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.650029 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 27.364617 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.639763 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.955624 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001670 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001382 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.958676 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15600 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 421 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2091 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5339 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5411 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2338 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.952148 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 401859473 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 401859473 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 287369 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155522 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 442891 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4441046 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4441046 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7316094 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7316094 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 640560 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 640560 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5011469 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5011469 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2961462 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2961462 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222733 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 222733 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 287369 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155522 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5011469 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3602022 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9056382 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 287369 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155522 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5011469 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3602022 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9056382 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20057 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9858 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 29915 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137835 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 137835 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154814 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 154814 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 699738 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 699738 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 498672 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 498672 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1226274 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1226274 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601108 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 601108 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20057 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9858 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 498672 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1926012 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2454599 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20057 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9858 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 498672 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1926012 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2454599 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 307426 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165380 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 472806 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4441046 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4441046 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7316094 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7316094 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137835 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 137835 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154814 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 154814 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510141 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5510141 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187736 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4187736 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 307426 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165380 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5510141 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5528034 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11510981 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 307426 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165380 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5510141 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5528034 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11510981 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059608 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.063271 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 15660.837363 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.957912 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.889938 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.955862 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001890 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001214 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.958965 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15585 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2073 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5396 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2374 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.951233 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 396876772 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 396876772 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 281069 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 152429 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 433498 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4385344 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4385344 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7228256 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7228256 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 628811 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 628811 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4957899 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4957899 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2920611 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2920611 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 215443 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 215443 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 281069 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 152429 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4957899 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3549422 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8940819 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 281069 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 152429 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4957899 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3549422 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8940819 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20714 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10073 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 30787 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134964 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 134964 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 151036 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 151036 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698165 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 698165 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 488475 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 488475 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1209294 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1209294 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 599506 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 599506 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20714 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10073 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 488475 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1907459 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2426721 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20714 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10073 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 488475 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1907459 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2426721 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 301783 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 162502 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 464285 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4385344 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4385344 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7228256 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7228256 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134964 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 134964 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 151036 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 151036 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1326976 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1326976 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5446374 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5446374 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4129905 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4129905 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 814949 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 814949 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 301783 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 162502 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5446374 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5456881 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11367540 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 301783 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 162502 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5446374 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5456881 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11367540 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061987 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.066311 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.522076 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.522076 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090501 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090501 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292825 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292825 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729641 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729641 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059608 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090501 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.348408 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213240 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059608 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090501 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.348408 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213240 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526132 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526132 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089688 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089688 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292814 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292814 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.735636 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.735636 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061987 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089688 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349551 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213478 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061987 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089688 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349551 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213478 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1552940 # number of writebacks -system.cpu0.l2cache.writebacks::total 1552940 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 24175638 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12313629 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 303605 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 303605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.writebacks::writebacks 1537445 # number of writebacks +system.cpu0.l2cache.writebacks::total 1537445 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 23876126 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12158327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 304592 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 304592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10320494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4441046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7317492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 137835 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154814 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 292649 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187736 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616156 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19670562 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37379570 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705437460 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753923068 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1463731936 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4670427 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 101174852 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 29058250 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.019576 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.138538 # Request fanout histogram +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 614484 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10190763 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4385344 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7229636 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 134964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 151036 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 286000 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1326976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1326976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5446374 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4129905 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 814949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 814949 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16424855 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19414693 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 360152 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 717544 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 36917244 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 697275284 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 744257581 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1440608 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2870176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1445843649 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4732413 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 102900484 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 28818191 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.019582 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.138557 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28489407 98.04% 98.04% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 568843 1.96% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28253885 98.04% 98.04% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 564306 1.96% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 29058250 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 28818191 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -700,47 +701,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 144363 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 145570 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 145570 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 145570 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 145570 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 145570 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 112948 88.82% 88.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14218 11.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 127166 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145570 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145570 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 127166 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 127166 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 272736 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90656208 # DTB read hits -system.cpu1.dtb.read_misses 111973 # DTB read misses -system.cpu1.dtb.write_hits 81688076 # DTB write hits -system.cpu1.dtb.write_misses 32390 # DTB write misses +system.cpu1.dtb.read_hits 92188600 # DTB read hits +system.cpu1.dtb.read_misses 112898 # DTB read misses +system.cpu1.dtb.write_hits 82869602 # DTB write hits +system.cpu1.dtb.write_misses 32672 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44985 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4483 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90768181 # DTB read accesses -system.cpu1.dtb.write_accesses 81720466 # DTB write accesses +system.cpu1.dtb.perms_faults 11594 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92301498 # DTB read accesses +system.cpu1.dtb.write_accesses 82902274 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172344284 # DTB hits -system.cpu1.dtb.misses 144363 # DTB misses -system.cpu1.dtb.accesses 172488647 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 175058202 # DTB hits +system.cpu1.dtb.misses 145570 # DTB misses +system.cpu1.dtb.accesses 175203772 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -770,469 +771,471 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 61351 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 62174 # Table walker walks requested +system.cpu1.itb.walker.walksLong 62174 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 62174 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 62174 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 62174 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 55194 99.03% 99.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 542 0.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55736 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62174 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62174 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 480862179 # ITB inst hits -system.cpu1.itb.inst_misses 61351 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55736 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55736 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117910 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 488205248 # ITB inst hits +system.cpu1.itb.inst_misses 62174 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31602 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses -system.cpu1.itb.hits 480862179 # DTB hits -system.cpu1.itb.misses 61351 # DTB misses -system.cpu1.itb.accesses 480923530 # DTB accesses -system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 488267422 # ITB inst accesses +system.cpu1.itb.hits 488205248 # DTB hits +system.cpu1.itb.misses 62174 # DTB misses +system.cpu1.itb.accesses 488267422 # DTB accesses +system.cpu1.numPwrStateTransitions 12500 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6250 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7502374904.322560 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 140163345879.751923 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4511 72.18% 72.18% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1712 27.39% 99.57% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.11% 99.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.05% 99.76% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94592569622 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7033264907012 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6250 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 287230675984 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46889843152016 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94354153907 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed -system.cpu1.committedInsts 480611396 # Number of instructions committed -system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses -system.cpu1.num_func_calls 28363152 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls -system.cpu1.num_int_insts 519092247 # number of integer instructions -system.cpu1.num_fp_insts 374666 # number of float instructions -system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read -system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written -system.cpu1.num_mem_refs 172465256 # number of memory refs -system.cpu1.num_load_insts 90755131 # Number of load instructions -system.cpu1.num_store_insts 81710125 # Number of store instructions -system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles -system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles -system.cpu1.Branches 107067845 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6250 # number of quiesce instructions executed +system.cpu1.committedInsts 487952717 # Number of instructions committed +system.cpu1.committedOps 574148180 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 526945204 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 380393 # Number of float alu accesses +system.cpu1.num_func_calls 28766283 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 74749330 # number of instructions that are conditional controls +system.cpu1.num_int_insts 526945204 # number of integer instructions +system.cpu1.num_fp_insts 380393 # number of float instructions +system.cpu1.num_int_register_reads 777937433 # number of times the integer registers were read +system.cpu1.num_int_register_writes 419402413 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 618522 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 309432 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 129016491 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 128726040 # number of times the CC registers were written +system.cpu1.num_mem_refs 175180123 # number of memory refs +system.cpu1.num_load_insts 92288401 # Number of load instructions +system.cpu1.num_store_insts 82891722 # Number of store instructions +system.cpu1.num_idle_cycles 93779692516.971710 # Number of idle cycles +system.cpu1.num_busy_cycles 574461390.028282 # Number of busy cycles +system.cpu1.not_idle_fraction 0.006088 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.993912 # Percentage of idle cycles +system.cpu1.Branches 108727125 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMisc 36628 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 90705162 16.03% 85.55% # Class of executed instruction -system.cpu1.op_class::MemWrite 81422056 14.39% 99.94% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 49969 0.01% 99.95% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 288069 0.05% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 398021787 69.29% 69.29% # Class of executed instruction +system.cpu1.op_class::IntMult 1155567 0.20% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 62024 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMisc 37076 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::MemRead 92237466 16.06% 85.56% # Class of executed instruction +system.cpu1.op_class::MemWrite 82599340 14.38% 99.94% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 50935 0.01% 99.95% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 292382 0.05% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 565908654 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5970884 # number of replacements -system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 166384448 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5971395 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.863581 # Average number of references to valid blocks. +system.cpu1.op_class::total 574456577 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 6056013 # number of replacements +system.cpu1.dcache.tags.tagsinuse 439.385542 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 169014740 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 6056525 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.906223 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.385542 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858175 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.858175 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 350957211 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 350957211 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 84198598 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84198598 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77531561 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77531561 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64886 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 64886 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055500 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2055500 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044725 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2044725 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 161795045 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 161795045 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 161982308 # number of overall hits -system.cpu1.dcache.overall_hits::total 161982308 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3367290 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3367290 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1466124 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1466124 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433871 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 433871 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147105 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 147105 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156674 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 156674 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5267285 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5267285 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6060908 # number of overall misses -system.cpu1.dcache.overall_misses::total 6060908 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018559 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018559 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869905 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869905 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066787 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066787 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071170 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071170 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031529 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031529 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036068 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036068 # miss rate for overall accesses +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 356467951 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 356467951 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 85651314 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 85651314 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 78663816 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 78663816 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189367 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 189367 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 66166 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 66166 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2074874 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2074874 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2069738 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2069738 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 164381296 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 164381296 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 164570663 # number of overall hits +system.cpu1.dcache.overall_hits::total 164570663 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3417226 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3417226 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1481686 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1481686 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 799274 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 799274 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443256 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 443256 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150141 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 150141 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 154039 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 154039 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5342168 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5342168 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6141442 # number of overall misses +system.cpu1.dcache.overall_misses::total 6141442 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 89068540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 89068540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 80145502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 80145502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 988641 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 988641 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 509422 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 509422 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2225015 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2225015 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2223777 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2223777 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 169723464 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 169723464 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 170712105 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 170712105 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038366 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038366 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018487 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018487 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808457 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808457 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870116 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870116 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067479 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067479 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069269 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069269 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031476 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031476 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035975 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035975 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5970884 # number of writebacks -system.cpu1.dcache.writebacks::total 5970884 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4768482 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. +system.cpu1.dcache.writebacks::writebacks 6056013 # number of writebacks +system.cpu1.dcache.writebacks::total 6056013 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4848965 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.412961 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 483411507 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4849477 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.683225 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412961 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits -system.cpu1.icache.overall_hits::total 476148096 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses -system.cpu1.icache.overall_misses::total 4768994 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 981371445 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 981371445 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 483411507 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 483411507 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 483411507 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 483411507 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 483411507 # number of overall hits +system.cpu1.icache.overall_hits::total 483411507 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4849477 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4849477 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4849477 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4849477 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4849477 # number of overall misses +system.cpu1.icache.overall_misses::total 4849477 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 488260984 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 488260984 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 488260984 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 488260984 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 488260984 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 488260984 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009932 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009932 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009932 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009932 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009932 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009932 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks -system.cpu1.icache.writebacks::total 4768482 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 4848965 # number of writebacks +system.cpu1.icache.writebacks::total 4848965 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2174770 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13105.960937 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8815603 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2190453 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.024557 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2230269 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13059.321303 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8938644 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2245943 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.979907 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.863128 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.242032 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.797660 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001334 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000930 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.799924 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15593 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 57 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2414 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3564 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1751 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 369059783 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 369059783 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 338101 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153667 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 491768 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4061526 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4061526 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6677473 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6677473 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614785 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614785 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4308825 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4308825 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3093892 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3093892 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164960 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 164960 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 338101 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153667 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4308825 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3708677 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8509270 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 338101 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153667 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4308825 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3708677 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8509270 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22355 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10972 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 33327 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145242 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 145242 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156674 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 156674 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 706301 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 706301 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 460169 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 460169 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1214126 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1214126 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268707 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 268707 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22355 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10972 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 460169 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1920427 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2413923 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22355 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10972 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 460169 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1920427 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2413923 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360456 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164639 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 525095 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4061526 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4061526 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6677473 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6677473 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145242 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 145242 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156674 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 156674 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308018 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4308018 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360456 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164639 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5629104 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10923193 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360456 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164639 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5629104 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10923193 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.066643 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.063469 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 13021.698131 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.453000 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.170172 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.794781 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001309 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000987 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.797078 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15589 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2501 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7586 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3485 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1787 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951477 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 374536552 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 374536552 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 340661 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155597 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 496258 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4122422 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4122422 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6782171 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6782171 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 622232 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 622232 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4374488 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4374488 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3137655 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3137655 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166849 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 166849 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 340661 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155597 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4374488 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3759887 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8630633 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 340661 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155597 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4374488 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3759887 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8630633 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22356 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11279 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 33635 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145163 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 145163 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154039 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 154039 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 714291 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 714291 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 474989 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 474989 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1228986 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1228986 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 276407 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 276407 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22356 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11279 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 474989 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1943277 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2451901 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22356 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11279 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 474989 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1943277 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2451901 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 363017 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166876 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 529893 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4122422 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4122422 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6782171 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6782171 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145163 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 145163 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 154039 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 154039 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1336523 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1336523 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4849477 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4849477 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4366641 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4366641 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443256 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 443256 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 363017 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 166876 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4849477 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5703164 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11082534 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 363017 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 166876 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4849477 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5703164 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11082534 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067589 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.063475 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534637 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534637 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096492 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096492 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281829 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281829 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.619616 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.619616 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.066643 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096492 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341160 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.220991 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.066643 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096492 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341160 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.220991 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534440 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534440 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097946 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097946 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281449 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281449 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.623583 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.623583 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.067589 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097946 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340737 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.221240 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.067589 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097946 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340737 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.221240 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1197912 # number of writebacks -system.cpu1.l2cache.writebacks::total 1197912 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22146544 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314780 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 285761 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 285759 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9684673 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4061526 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6677840 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 145242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156674 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 301916 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308018 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18723008 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34233178 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432559 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1357645303 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4277162 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 79243712 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 26604267 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.021049 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.143548 # Request fanout histogram +system.cpu1.l2cache.writebacks::writebacks 1226637 # number of writebacks +system.cpu1.l2cache.writebacks::total 1226637 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22478068 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11482434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 282472 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 282472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 614190 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9830308 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6354 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6354 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4122422 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6782556 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 145163 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 154039 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 299202 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1336523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1336523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4849477 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4366641 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 443256 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 443256 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14548179 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18972689 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371656 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 843740 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34736264 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 620700808 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 752625722 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1486624 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3374960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1378188114 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4390439 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 84812544 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 27053766 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.020745 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.142530 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26044274 97.90% 97.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 559991 2.10% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26492533 97.93% 97.93% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 561233 2.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 26604267 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40301 # Transaction distribution -system.iobus.trans_dist::ReadResp 40301 # Transaction distribution -system.iobus.trans_dist::WriteReq 136636 # Transaction distribution -system.iobus.trans_dist::WriteResp 136636 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 27053766 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40293 # Transaction distribution +system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.trans_dist::WriteReq 136632 # Transaction distribution +system.iobus.trans_dist::WriteResp 136632 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47630 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1245,13 +1248,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47650 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1264,56 +1267,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155671 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115590 # number of replacements -system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use +system.iobus.pkt_size::total 7496597 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115584 # number of replacements +system.iocache.tags.tagsinuse 11.285245 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115600 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.859437 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.425808 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.241215 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464113 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705328 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040838 # Number of tag accesses -system.iocache.tags.data_accesses 1040838 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040784 # Number of tag accesses +system.iocache.tags.data_accesses 1040784 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses -system.iocache.demand_misses::total 115649 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses +system.iocache.demand_misses::total 115643 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115609 # number of overall misses -system.iocache.overall_misses::total 115649 # number of overall misses +system.iocache.overall_misses::realview.ide 115603 # number of overall misses +system.iocache.overall_misses::total 115643 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1335,279 +1338,280 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1924793 # number of replacements -system.l2c.tags.tagsinuse 65250.197909 # Cycle average of tags in use -system.l2c.tags.total_refs 5713780 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1986359 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.876509 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1923250 # number of replacements +system.l2c.tags.tagsinuse 65186.498545 # Cycle average of tags in use +system.l2c.tags.total_refs 5749330 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1985687 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.895386 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10662.392220 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 41.728586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 44.787257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3175.849688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 15990.343630 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 362.595804 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 421.087250 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2804.760651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 31746.652822 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.162695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000637 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000683 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048460 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.243993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006425 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.484415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995639 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 224 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61342 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 10983.634083 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.375221 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 60.020702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3162.214163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16603.028209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 344.016385 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 410.384147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2922.724883 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 30643.100751 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.167597 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.048252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.253342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006262 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.044597 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.467577 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994667 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62196 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 223 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3566 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.936005 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 71904156 # Number of tag accesses -system.l2c.tags.data_accesses 71904156 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2750852 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2750852 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 60132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 51539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 111671 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8500 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7695 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16195 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 199510 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 176557 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 376067 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12368 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5246 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 435137 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 707607 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12105 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4097 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 413141 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 664483 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2254184 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 130356 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 113567 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 243923 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5246 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 435137 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 907117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12105 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 413141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 841040 # number of demand (read+write) hits -system.l2c.demand_hits::total 2630251 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12368 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5246 # number of overall hits -system.l2c.overall_hits::cpu0.inst 435137 # number of overall hits -system.l2c.overall_hits::cpu0.data 907117 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12105 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4097 # number of overall hits -system.l2c.overall_hits::cpu1.inst 413141 # number of overall hits -system.l2c.overall_hits::cpu1.data 841040 # number of overall hits -system.l2c.overall_hits::total 2630251 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 21889 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 25427 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 47316 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 415 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 794 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1209 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 372583 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 420111 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 792694 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2419 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2002 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 63535 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 191729 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3502 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3484 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 47028 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 197713 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 511412 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 462716 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 149158 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 611874 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2419 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2002 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 63535 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 564312 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3502 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47028 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 617824 # number of demand (read+write) misses -system.l2c.demand_misses::total 1304106 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2419 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2002 # number of overall misses -system.l2c.overall_misses::cpu0.inst 63535 # number of overall misses -system.l2c.overall_misses::cpu0.data 564312 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3502 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3484 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47028 # number of overall misses -system.l2c.overall_misses::cpu1.data 617824 # number of overall misses -system.l2c.overall_misses::total 1304106 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2750852 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2750852 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 82021 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 76966 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158987 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 8915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8489 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17404 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 572093 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 596668 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1168761 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14787 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7248 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 498672 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 899336 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15607 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7581 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 460169 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 862196 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2765596 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 593072 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 262725 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 855797 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 14787 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 498672 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1471429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 15607 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7581 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 460169 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1458864 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3934357 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 14787 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 498672 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1471429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15607 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7581 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 460169 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1458864 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3934357 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266871 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330367 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.297609 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.046551 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.093533 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.069467 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.651263 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.704095 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.678234 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276214 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.127408 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213190 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.459570 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.102197 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.229313 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.184919 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.780202 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.567734 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.714976 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.276214 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.127408 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.383513 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.459570 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.102197 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.423497 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.331466 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.276214 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.127408 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.383513 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.459570 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.102197 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.423497 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.331466 # miss rate for overall accesses +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3250 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4725 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53923 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.949036 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 71541788 # Number of tag accesses +system.l2c.tags.data_accesses 71541788 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2764082 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2764082 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 56104 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 51044 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 107148 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8413 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7881 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16294 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 200040 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 182839 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 382879 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12914 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5340 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 425659 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 696237 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12397 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4498 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 426584 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 681796 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2265425 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 112817 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 103406 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 216223 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 12914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5340 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 425659 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 896277 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12397 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 426584 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 864635 # number of demand (read+write) hits +system.l2c.demand_hits::total 2648304 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 12914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5340 # number of overall hits +system.l2c.overall_hits::cpu0.inst 425659 # number of overall hits +system.l2c.overall_hits::cpu0.data 896277 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12397 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4498 # number of overall hits +system.l2c.overall_hits::cpu1.inst 426584 # number of overall hits +system.l2c.overall_hits::cpu1.data 864635 # number of overall hits +system.l2c.overall_hits::total 2648304 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 19306 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 23056 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 42362 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 403 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 802 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 372703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 418393 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 791096 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2468 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2058 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 62816 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 191372 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3475 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3462 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 48405 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 197388 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 511444 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 440136 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 128597 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 568733 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2468 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2058 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 62816 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 564075 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3475 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 48405 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 615781 # number of demand (read+write) misses +system.l2c.demand_misses::total 1302540 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2468 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2058 # number of overall misses +system.l2c.overall_misses::cpu0.inst 62816 # number of overall misses +system.l2c.overall_misses::cpu0.data 564075 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3475 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses +system.l2c.overall_misses::cpu1.inst 48405 # number of overall misses +system.l2c.overall_misses::cpu1.data 615781 # number of overall misses +system.l2c.overall_misses::total 1302540 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2764082 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2764082 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 75410 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 74100 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 149510 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 8816 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8683 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17499 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 572743 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 601232 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1173975 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15382 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7398 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 488475 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 887609 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15872 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7960 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 474989 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 879184 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2776869 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 552953 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 232003 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 784956 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 15382 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 488475 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1460352 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 15872 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7960 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 474989 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1480416 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3950844 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 15382 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 488475 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1460352 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 15872 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7960 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 474989 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1480416 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3950844 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.256014 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311147 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.283339 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045712 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.092364 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.068861 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.650733 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.695893 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.673861 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.278183 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.128596 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215604 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.434925 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.101908 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.224513 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.184180 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.795974 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.554290 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.724541 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.278183 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.128596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.386260 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.434925 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.101908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.415951 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.329687 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.278183 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.128596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.386260 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.434925 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.101908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.415951 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.329687 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1492845 # number of writebacks -system.l2c.writebacks::total 1492845 # number of writebacks -system.membus.snoop_filter.tot_requests 4436915 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2508187 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1489052 # number of writebacks +system.l2c.writebacks::total 1489052 # number of writebacks +system.membus.snoop_filter.tot_requests 4378272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2451994 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3422 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 82130 # Transaction distribution -system.membus.trans_dist::ReadResp 602460 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 82126 # Transaction distribution +system.membus.trans_dist::ReadResp 602482 # Transaction distribution system.membus.trans_dist::WriteReq 38798 # Transaction distribution system.membus.trans_dist::WriteResp 38798 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1599539 # Transaction distribution -system.membus.trans_dist::CleanEvict 267122 # Transaction distribution -system.membus.trans_dist::UpgradeReq 245150 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 295293 # Transaction distribution -system.membus.trans_dist::UpgradeResp 53835 # Transaction distribution -system.membus.trans_dist::ReadExReq 792754 # Transaction distribution -system.membus.trans_dist::ReadExResp 789263 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 520330 # Transaction distribution -system.membus.trans_dist::InvalidateReq 716726 # Transaction distribution -system.membus.trans_dist::InvalidateResp 716726 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::WritebackDirty 1595746 # Transaction distribution +system.membus.trans_dist::CleanEvict 267406 # Transaction distribution +system.membus.trans_dist::UpgradeReq 230305 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 288781 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46602 # Transaction distribution +system.membus.trans_dist::ReadExReq 791817 # Transaction distribution +system.membus.trans_dist::ReadExResp 788064 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 520356 # Transaction distribution +system.membus.trans_dist::InvalidateReq 683860 # Transaction distribution +system.membus.trans_dist::InvalidateResp 675461 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122564 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6261826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6412036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6758924 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6153530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6303732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6650602 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155671 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178979036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 179190007 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 186589175 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178661596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 178872563 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7398784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 186271347 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4557842 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007340 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.085359 # Request fanout histogram +system.membus.snoop_fanout::samples 4499195 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007389 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.085643 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4524387 99.27% 99.27% # Request fanout histogram -system.membus.snoop_fanout::1 33455 0.73% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4465949 99.26% 99.26% # Request fanout histogram +system.membus.snoop_fanout::1 33246 0.74% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4557842 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4499195 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1617,11 +1621,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1650,68 +1654,68 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11075061 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5706480 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1648775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 269190 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 248390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 20800 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3544615 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11103133 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5636149 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1803428 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 289976 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 265298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 24678 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 82128 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3548294 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2750852 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1991304 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 351511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 311488 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 662999 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1351623 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1351623 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3462483 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 855797 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 855797 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9483041 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8166779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17649820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254997904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229564151 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 484562055 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1959256 # Total snoops (count) -system.toL2Bus.snoopTraffic 95582592 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 13153559 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.293824 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.458971 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 2764082 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1999311 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 334418 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 305075 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 639493 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1358165 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1358165 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3466166 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 875913 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 875913 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9373855 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8310864 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17684719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252267457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 233795714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 486063171 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1971827 # Total snoops (count) +system.toL2Bus.snoopTraffic 95347072 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13179862 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.305132 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.464512 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9309527 70.78% 70.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3823232 29.07% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 20800 0.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9182942 69.67% 69.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3972242 30.14% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 24678 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13153559 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13179862 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 62bebe0c3..203bf8cf0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167268500 # Number of ticks simulated -final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.548252 # Number of seconds simulated +sim_ticks 51548252400500 # Number of ticks simulated +final_tick 51548252400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1788186 # Simulator instruction rate (inst/s) -host_op_rate 2101506 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93052770956 # Simulator tick rate (ticks/s) -host_mem_usage 679348 # Number of bytes of host memory used -host_seconds 549.27 # Real time elapsed on the host -sim_insts 982198023 # Number of instructions simulated -sim_ops 1154295627 # Number of ops (including micro ops) simulated +host_inst_rate 1717705 # Simulator instruction rate (inst/s) +host_op_rate 1880520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48787200192 # Simulator tick rate (ticks/s) +host_mem_usage 679528 # Number of bytes of host memory used +host_seconds 1056.59 # Real time elapsed on the host +sim_insts 1814916572 # Number of instructions simulated +sim_ops 1986945286 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 388608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 367808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5292340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 73326152 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 442368 # Number of bytes read from this memory +system.physmem.bytes_read::total 79817276 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5292340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5292340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101858624 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101879204 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 123100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1145734 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6912 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1287565 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1591541 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.physmem.num_writes::total 1594114 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 102668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1422476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1548399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1975986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1976385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1975986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1422875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3524784 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,47 +109,47 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 266581 # Table walker walks requested -system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 267664 # Table walker walks requested +system.cpu.dtb.walker.walksLong 267664 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 267664 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 267664 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 267664 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 206672 89.75% 89.75% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23595 10.25% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 230267 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 267664 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 267664 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 230267 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 230267 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 497931 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183543984 # DTB read hits -system.cpu.dtb.read_misses 195343 # DTB read misses -system.cpu.dtb.write_hits 167774645 # DTB write hits -system.cpu.dtb.write_misses 71238 # DTB write misses +system.cpu.dtb.read_hits 421603994 # DTB read hits +system.cpu.dtb.read_misses 196270 # DTB read misses +system.cpu.dtb.write_hits 167651282 # DTB write hits +system.cpu.dtb.write_misses 71394 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 81418 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9097 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183739327 # DTB read accesses -system.cpu.dtb.write_accesses 167845883 # DTB write accesses +system.cpu.dtb.perms_faults 21656 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 421800264 # DTB read accesses +system.cpu.dtb.write_accesses 167722676 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351318629 # DTB hits -system.cpu.dtb.misses 266581 # DTB misses -system.cpu.dtb.accesses 351585210 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 589255276 # DTB hits +system.cpu.dtb.misses 267664 # DTB misses +system.cpu.dtb.accesses 589522940 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,52 +179,52 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126834 # Table walker walks requested -system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 126885 # Table walker walks requested +system.cpu.itb.walker.walksLong 126885 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126885 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126885 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126885 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113624 99.02% 99.02% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114746 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126885 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126885 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982674869 # ITB inst hits -system.cpu.itb.inst_misses 126834 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114746 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114746 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241631 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 1815394284 # ITB inst hits +system.cpu.itb.inst_misses 126885 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57333 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982801703 # ITB inst accesses -system.cpu.itb.hits 982674869 # DTB hits -system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982801703 # DTB accesses -system.cpu.numPwrStateTransitions 33550 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 1815521169 # ITB inst accesses +system.cpu.itb.hits 1815394284 # DTB hits +system.cpu.itb.misses 126885 # DTB misses +system.cpu.itb.accesses 1815521169 # DTB accesses +system.cpu.numPwrStateTransitions 33574 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16787 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3011524161.053136 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59680214632.955681 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7463 44.46% 44.46% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9289 55.33% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state @@ -232,413 +232,414 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351313 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16787 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 993796308901 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50554456091599 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103096521589 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982198023 # Number of instructions committed -system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56833843 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057877135 # number of integer instructions -system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read -system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read -system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written -system.cpu.num_mem_refs 351538055 # number of memory refs -system.cpu.num_load_insts 183711282 # Number of load instructions -system.cpu.num_store_insts 167826773 # Number of store instructions -system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles -system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles -system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219532189 # Number of branches fetched +system.cpu.kern.inst.quiesce 16787 # number of quiesce instructions executed +system.cpu.committedInsts 1814916572 # Number of instructions committed +system.cpu.committedOps 1986945286 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1711962456 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 884728 # Number of float alu accesses +system.cpu.num_func_calls 56754008 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 449117161 # number of instructions that are conditional controls +system.cpu.num_int_insts 1711962456 # number of integer instructions +system.cpu.num_fp_insts 884728 # number of float instructions +system.cpu.num_int_register_reads 2333816547 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316284167 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1424283 # number of times the floating registers were read +system.cpu.num_fp_register_writes 753044 # number of times the floating registers were written +system.cpu.num_cc_register_reads 621173289 # number of times the CC registers were read +system.cpu.num_cc_register_writes 620585461 # number of times the CC registers were written +system.cpu.num_mem_refs 589476099 # number of memory refs +system.cpu.num_load_insts 421772480 # Number of load instructions +system.cpu.num_store_insts 167703619 # Number of store instructions +system.cpu.num_idle_cycles 101108928647.540985 # Number of idle cycles +system.cpu.num_busy_cycles 1987592941.459016 # Number of busy cycles +system.cpu.not_idle_fraction 0.019279 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.980721 # Percentage of idle cycles +system.cpu.Branches 576475057 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMisc 107822 0.01% 69.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183598958 15.90% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 167165612 14.47% 99.93% # Class of executed instruction -system.cpu.op_class::FloatMemRead 112324 0.01% 99.94% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 661161 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1395540402 70.21% 70.21% # Class of executed instruction +system.cpu.op_class::IntMult 2356131 0.12% 70.33% # Class of executed instruction +system.cpu.op_class::IntDiv 100370 0.01% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMisc 107824 0.01% 70.34% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::MemRead 421659035 21.21% 91.56% # Class of executed instruction +system.cpu.op_class::MemWrite 167040202 8.40% 99.96% # Class of executed instruction +system.cpu.op_class::FloatMemRead 113445 0.01% 99.97% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 663417 0.03% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154930294 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11606056 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. +system.cpu.op_class::total 1987580869 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11603445 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999721 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 577795083 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11603957 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 49.792936 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999721 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits -system.cpu.dcache.overall_hits::total 330960928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 2369200172 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2369200172 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 409181313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 409181313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158964390 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158964390 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 425694 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 425694 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336647 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336647 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4299455 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4299455 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4553147 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4553147 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 568482350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568482350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568908044 # number of overall hits +system.cpu.dcache.overall_hits::total 568908044 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5993326 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5993326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2556217 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2556217 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586747 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586747 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246619 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246619 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 255495 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 255495 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses -system.cpu.dcache.overall_misses::total 11387343 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 9796162 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9796162 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11382909 # number of overall misses +system.cpu.dcache.overall_misses::total 11382909 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 415174639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415174639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161520607 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161520607 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2012441 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2012441 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583266 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1583266 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4554950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4554950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4553148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4553148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 578278512 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 578278512 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 580290953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 580290953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.014436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015826 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015826 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788469 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788469 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787372 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787372 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056092 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056092 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019616 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019616 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks -system.cpu.dcache.writebacks::total 8918956 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265255 # number of replacements -system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. +system.cpu.dcache.writebacks::writebacks 8939334 # number of writebacks +system.cpu.dcache.writebacks::total 8939334 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14289332 # number of replacements +system.cpu.icache.tags.tagsinuse 511.984730 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1801219181 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14289844 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 126.048904 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.984730 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits -system.cpu.icache.overall_hits::total 968523793 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses -system.cpu.icache.overall_misses::total 14265772 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 1829798879 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1829798879 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1801219181 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1801219181 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1801219181 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1801219181 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1801219181 # number of overall hits +system.cpu.icache.overall_hits::total 1801219181 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14289849 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14289849 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14289849 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14289849 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14289849 # number of overall misses +system.cpu.icache.overall_misses::total 14289849 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 1815509030 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1815509030 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1815509030 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1815509030 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1815509030 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1815509030 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007871 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007871 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007871 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007871 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007871 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007871 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks -system.cpu.icache.writebacks::total 14265255 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1725823 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks. +system.cpu.icache.writebacks::writebacks 14289332 # number of writebacks +system.cpu.icache.writebacks::total 14289332 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1684196 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65394.978455 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 49472483 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1746767 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.322314 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits -system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 9677.706964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 426.448625 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 480.005287 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6101.422178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48709.395401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.147670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006507 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007324 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.743246 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 329 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62242 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 328 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1404 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5082 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55348 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005020 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 422888423 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 422888423 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 482010 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237204 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 719214 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8939334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8939334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14287756 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14287756 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 30651 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 30651 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1695121 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1695121 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14209837 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14209837 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7515311 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7515311 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 704740 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 704740 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 482010 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 237204 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14209837 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9210432 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24139483 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 482010 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 237204 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14209837 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9210432 # number of overall hits +system.cpu.l2cache.overall_hits::total 24139483 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6072 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5747 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 11819 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3785 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3785 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 826660 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826660 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80012 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 80012 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320257 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 320257 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 541879 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 541879 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6072 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5747 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 80012 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1146917 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1238748 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6072 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5747 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 80012 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1146917 # number of overall misses +system.cpu.l2cache.overall_misses::total 1238748 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 488082 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 242951 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 731033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8939334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8939334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14287756 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14287756 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34436 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 34436 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2521781 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2521781 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14289849 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14289849 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7835568 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7835568 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246619 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1246619 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 488082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 242951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14289849 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10357349 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25378231 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 488082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 242951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14289849 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10357349 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25378231 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012441 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.023655 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016168 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109914 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109914 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327808 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.327808 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040872 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040872 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.434679 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.434679 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.023655 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.110735 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.048811 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.023655 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.110735 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.048811 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks -system.cpu.l2cache.writebacks::total 1507096 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1484910 # number of writebacks +system.cpu.l2cache.writebacks::total 1484910 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 52410934 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26517119 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2740 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1234221 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23359638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8939334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14289332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2664111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 34436 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 34437 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2521781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2521781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14289849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7835568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1246619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1246619 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42955280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35014647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1556522 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80284963 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829240084 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235177526 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3034056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6226088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3073677754 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1724598 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 95094976 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 54812635 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010876 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103719 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54216500 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596135 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40242 # Transaction distribution -system.iobus.trans_dist::ReadResp 40242 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 54812635 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40253 # Transaction distribution +system.iobus.trans_dist::ReadResp 40253 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -655,11 +656,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353536 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -674,55 +675,55 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use +system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115470 # number of replacements +system.iocache.tags.tagsinuse 10.454534 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.524459 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.930076 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220279 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433130 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653408 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses -system.iocache.demand_misses::total 115517 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses +system.iocache.demand_misses::total 115528 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115477 # number of overall misses -system.iocache.overall_misses::total 115517 # number of overall misses +system.iocache.overall_misses::realview.ide 115488 # number of overall misses +system.iocache.overall_misses::total 115528 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -744,71 +745,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 3698370 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1836830 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524960 # Transaction distribution -system.membus.trans_dist::WriteReq 33606 # Transaction distribution -system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution -system.membus.trans_dist::CleanEvict 226320 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 76703 # Transaction distribution +system.membus.trans_dist::ReadResp 497652 # Transaction distribution +system.membus.trans_dist::WriteReq 33618 # Transaction distribution +system.membus.trans_dist::WriteResp 33618 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1591541 # Transaction distribution +system.membus.trans_dist::CleanEvict 206888 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4346 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution -system.membus.trans_dist::ReadExReq 827049 # Transaction distribution -system.membus.trans_dist::ReadExResp 827049 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4347 # Transaction distribution +system.membus.trans_dist::ReadExReq 826102 # Transaction distribution +system.membus.trans_dist::ReadExResp 826102 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420949 # Transaction distribution +system.membus.trans_dist::InvalidateReq 648543 # Transaction distribution +system.membus.trans_dist::InvalidateResp 648543 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6726 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5343163 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5472427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5818953 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 174471520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 174640714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 182032202 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3888979 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram +system.membus.snoop_fanout::samples 3808691 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010569 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.102262 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram -system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3768436 98.94% 98.94% # Request fanout histogram +system.membus.snoop_fanout::1 40255 1.06% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3888979 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3808691 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -818,11 +819,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -851,28 +852,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index fcaa09afa..529d7a06f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.405013 # Number of seconds simulated -sim_ticks 47405012960500 # Number of ticks simulated -final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.405081 # Number of seconds simulated +sim_ticks 47405080882500 # Number of ticks simulated +final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080699 # Simulator instruction rate (inst/s) -host_op_rate 1271286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58247547339 # Simulator tick rate (ticks/s) -host_mem_usage 759864 # Number of bytes of host memory used -host_seconds 813.85 # Real time elapsed on the host -sim_insts 879531552 # Number of instructions simulated -sim_ops 1034641707 # Number of ops (including micro ops) simulated +host_inst_rate 1071981 # Simulator instruction rate (inst/s) +host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57861452624 # Simulator tick rate (ticks/s) +host_mem_usage 765552 # Number of bytes of host memory used +host_seconds 819.29 # Real time elapsed on the host +sim_insts 878258906 # Number of instructions simulated +sim_ops 1033075205 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory -system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory +system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory -system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory +system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 927485 # Number of read requests accepted -system.physmem.writeReqs 1171828 # Number of write requests accepted -system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue -system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 927476 # Number of read requests accepted +system.physmem.writeReqs 1170446 # Number of write requests accepted +system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue +system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 53188 # Per bank write bursts -system.physmem.perBankRdBursts::1 58555 # Per bank write bursts -system.physmem.perBankRdBursts::2 49548 # Per bank write bursts -system.physmem.perBankRdBursts::3 58849 # Per bank write bursts -system.physmem.perBankRdBursts::4 61060 # Per bank write bursts -system.physmem.perBankRdBursts::5 64213 # Per bank write bursts -system.physmem.perBankRdBursts::6 58593 # Per bank write bursts -system.physmem.perBankRdBursts::7 62574 # Per bank write bursts -system.physmem.perBankRdBursts::8 53530 # Per bank write bursts -system.physmem.perBankRdBursts::9 96457 # Per bank write bursts -system.physmem.perBankRdBursts::10 50033 # Per bank write bursts -system.physmem.perBankRdBursts::11 57571 # Per bank write bursts -system.physmem.perBankRdBursts::12 47029 # Per bank write bursts -system.physmem.perBankRdBursts::13 51615 # Per bank write bursts -system.physmem.perBankRdBursts::14 49510 # Per bank write bursts -system.physmem.perBankRdBursts::15 54823 # Per bank write bursts -system.physmem.perBankWrBursts::0 69378 # Per bank write bursts -system.physmem.perBankWrBursts::1 74382 # Per bank write bursts -system.physmem.perBankWrBursts::2 69427 # Per bank write bursts -system.physmem.perBankWrBursts::3 75087 # Per bank write bursts -system.physmem.perBankWrBursts::4 76532 # Per bank write bursts -system.physmem.perBankWrBursts::5 78990 # Per bank write bursts -system.physmem.perBankWrBursts::6 75385 # Per bank write bursts -system.physmem.perBankWrBursts::7 77589 # Per bank write bursts -system.physmem.perBankWrBursts::8 70916 # Per bank write bursts -system.physmem.perBankWrBursts::9 76207 # Per bank write bursts -system.physmem.perBankWrBursts::10 70858 # Per bank write bursts -system.physmem.perBankWrBursts::11 75862 # Per bank write bursts -system.physmem.perBankWrBursts::12 66596 # Per bank write bursts -system.physmem.perBankWrBursts::13 70423 # Per bank write bursts -system.physmem.perBankWrBursts::14 68869 # Per bank write bursts -system.physmem.perBankWrBursts::15 73044 # Per bank write bursts +system.physmem.perBankRdBursts::0 53525 # Per bank write bursts +system.physmem.perBankRdBursts::1 58700 # Per bank write bursts +system.physmem.perBankRdBursts::2 53136 # Per bank write bursts +system.physmem.perBankRdBursts::3 59915 # Per bank write bursts +system.physmem.perBankRdBursts::4 57558 # Per bank write bursts +system.physmem.perBankRdBursts::5 67025 # Per bank write bursts +system.physmem.perBankRdBursts::6 57593 # Per bank write bursts +system.physmem.perBankRdBursts::7 57551 # Per bank write bursts +system.physmem.perBankRdBursts::8 45941 # Per bank write bursts +system.physmem.perBankRdBursts::9 94599 # Per bank write bursts +system.physmem.perBankRdBursts::10 49635 # Per bank write bursts +system.physmem.perBankRdBursts::11 57294 # Per bank write bursts +system.physmem.perBankRdBursts::12 48522 # Per bank write bursts +system.physmem.perBankRdBursts::13 56965 # Per bank write bursts +system.physmem.perBankRdBursts::14 52794 # Per bank write bursts +system.physmem.perBankRdBursts::15 56368 # Per bank write bursts +system.physmem.perBankWrBursts::0 71875 # Per bank write bursts +system.physmem.perBankWrBursts::1 75753 # Per bank write bursts +system.physmem.perBankWrBursts::2 71549 # Per bank write bursts +system.physmem.perBankWrBursts::3 77042 # Per bank write bursts +system.physmem.perBankWrBursts::4 73392 # Per bank write bursts +system.physmem.perBankWrBursts::5 80022 # Per bank write bursts +system.physmem.perBankWrBursts::6 71461 # Per bank write bursts +system.physmem.perBankWrBursts::7 73088 # Per bank write bursts +system.physmem.perBankWrBursts::8 65465 # Per bank write bursts +system.physmem.perBankWrBursts::9 74249 # Per bank write bursts +system.physmem.perBankWrBursts::10 70475 # Per bank write bursts +system.physmem.perBankWrBursts::11 74236 # Per bank write bursts +system.physmem.perBankWrBursts::12 69250 # Per bank write bursts +system.physmem.perBankWrBursts::13 75271 # Per bank write bursts +system.physmem.perBankWrBursts::14 70641 # Per bank write bursts +system.physmem.perBankWrBursts::15 74378 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 516 # Number of times write queue was full causing retry -system.physmem.totGap 47405009605000 # Total gap between requests +system.physmem.numWrRetry 399 # Number of times write queue was full causing retry +system.physmem.totGap 47405077592000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 884260 # Read request sizes (log2) +system.physmem.readPktSize::6 884251 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1169254 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1167872 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,129 +189,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads -system.physmem.totQLat 46218732203 # Total ticks spent queuing -system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads +system.physmem.totQLat 46391884854 # Total ticks spent queuing +system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s @@ -320,53 +303,53 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 685692 # Number of row buffer hits during reads -system.physmem.writeRowHits 481982 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes -system.physmem.avgGap 22581201.38 # Average gap between requests +system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 687053 # Number of row buffer hits during reads +system.physmem.writeRowHits 479716 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes +system.physmem.avgGap 22596205.96 # Average gap between requests system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.014314 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states -system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states -system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.859346 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states -system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states -system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.004907 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states +system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states +system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.918480 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states +system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states +system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -393,9 +376,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -403,7 +386,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -433,71 +416,72 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 110745 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 105104 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86849149 # DTB read hits -system.cpu0.dtb.read_misses 83538 # DTB read misses -system.cpu0.dtb.write_hits 78785461 # DTB write hits -system.cpu0.dtb.write_misses 27207 # DTB write misses +system.cpu0.dtb.read_hits 85250979 # DTB read hits +system.cpu0.dtb.read_misses 79026 # DTB read misses +system.cpu0.dtb.write_hits 77401552 # DTB write hits +system.cpu0.dtb.write_misses 26078 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86932687 # DTB read accesses -system.cpu0.dtb.write_accesses 78812668 # DTB write accesses +system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85330005 # DTB read accesses +system.cpu0.dtb.write_accesses 77427630 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165634610 # DTB hits -system.cpu0.dtb.misses 110745 # DTB misses -system.cpu0.dtb.accesses 165745355 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 162652531 # DTB hits +system.cpu0.dtb.misses 105104 # DTB misses +system.cpu0.dtb.accesses 162757635 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -527,763 +511,759 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57780 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 55600 # Table walker walks requested +system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 463942995 # ITB inst hits -system.cpu0.itb.inst_misses 57780 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 455710659 # ITB inst hits +system.cpu0.itb.inst_misses 55600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses -system.cpu0.itb.hits 463942995 # DTB hits -system.cpu0.itb.misses 57780 # DTB misses -system.cpu0.itb.accesses 464000775 # DTB accesses -system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses +system.cpu0.itb.hits 455710659 # DTB hits +system.cpu0.itb.misses 55600 # DTB misses +system.cpu0.itb.accesses 455766259 # DTB accesses +system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94810025915 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94809604801 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed -system.cpu0.committedInsts 463690677 # Number of instructions committed -system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses -system.cpu0.num_func_calls 27825312 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls -system.cpu0.num_int_insts 499985272 # number of integer instructions -system.cpu0.num_fp_insts 430429 # number of float instructions -system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read -system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written -system.cpu0.num_mem_refs 165624912 # number of memory refs -system.cpu0.num_load_insts 86844124 # Number of load instructions -system.cpu0.num_store_insts 78780788 # Number of store instructions -system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles -system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles -system.cpu0.Branches 103560532 # Number of branches fetched +system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed +system.cpu0.committedInsts 455440444 # Number of instructions committed +system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses +system.cpu0.num_func_calls 27345084 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 490602455 # number of integer instructions +system.cpu0.num_fp_insts 409464 # number of float instructions +system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read +system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written +system.cpu0.num_mem_refs 162644052 # number of memory refs +system.cpu0.num_load_insts 85246888 # Number of load instructions +system.cpu0.num_store_insts 77397164 # Number of store instructions +system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles +system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles +system.cpu0.Branches 101837898 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMisc 44848 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 86795135 15.94% 85.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 78444196 14.40% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 48989 0.01% 99.94% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 336592 0.06% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction +system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 544601223 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5731745 # number of replacements -system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. +system.cpu0.op_class::total 534571495 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5548235 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits -system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses -system.cpu0.dcache.overall_misses::total 5977347 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits +system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses +system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks -system.cpu0.dcache.writebacks::total 5731745 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks +system.cpu0.dcache.writebacks::total 5548235 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4959559 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4928137 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits -system.cpu0.icache.overall_hits::total 458982923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses -system.cpu0.icache.overall_misses::total 4960072 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits +system.cpu0.icache.overall_hits::total 450782010 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses +system.cpu0.icache.overall_misses::total 4928649 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks -system.cpu0.icache.writebacks::total 4959559 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks +system.cpu0.icache.writebacks::total 4928137 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2286879 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4608 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8403 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1616 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018677 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900696 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 368793343 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 368793343 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 252482 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 146217 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 398699 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3794669 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3794669 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 6895627 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 6895627 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 932984 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 932984 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4503327 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4503327 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2919116 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2919116 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 217183 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 217183 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 252482 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 146217 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4503327 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3852100 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8754126 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 252482 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 146217 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4503327 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3852100 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8754126 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 17757 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8990 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 26747 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 236502 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 236502 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 200518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 248602 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 248602 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 456745 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 456745 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 935783 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 935783 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577322 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 577322 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 17757 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8990 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 456745 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1184385 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1667877 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 17757 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8990 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 456745 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1184385 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1667877 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 557104000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 362043000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 919147000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 930109500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 930109500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 320714500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 320714500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2109497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2109497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13818048499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 13818048499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17338170000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17338170000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36151090000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36151090000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 305279500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 305279500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 557104000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 362043000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17338170000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 49969138499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 68226455499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 557104000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 362043000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17338170000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 49969138499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 68226455499 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 270239 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155207 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 425446 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3794669 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3794669 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 6895627 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 6895627 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 236502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200518 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 200518 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1181586 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1181586 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4960072 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 4960072 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3854899 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3854899 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794505 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 794505 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 270239 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155207 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4960072 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5036485 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 10422003 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 270239 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155207 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4960072 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5036485 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 10422003 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057923 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.062868 # miss rate for ReadReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2238289 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210397 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210397 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092084 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092084 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242752 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242752 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.726644 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.726644 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057923 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092084 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235161 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.160034 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057923 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092084 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235161 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.160034 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3932.776467 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3932.776467 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1599.429976 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1599.429976 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 528.785496 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 528.785496 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 38115 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1518116 # number of writebacks -system.cpu0.l2cache.writebacks::total 1518116 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6419 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 6419 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 459 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 459 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6878 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6878 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6878 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6878 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 17757 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8990 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 26747 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 749864 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 236502 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 236502 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200518 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200518 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 242183 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 242183 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 456745 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 456745 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 935324 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 935324 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577322 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577322 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 17757 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8990 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 456745 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1177507 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1660999 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 17757 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8990 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 456745 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1177507 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2410863 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks +system.cpu0.l2cache.writebacks::total 1501692 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59506 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77200 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308103000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 758665000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37032584946 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4392780000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4392780000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3053423000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3053423000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1785497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1785497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11646133999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11646133999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14597700000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14597700000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30480683500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30480683500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18786696000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18786696000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308103000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14597700000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42126817499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 57483182499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308103000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14597700000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42126817499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 94515767445 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2909184500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6702281000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2909184500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1292,124 +1272,123 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,71 +1418,72 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 99152 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 105151 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78885011 # DTB read hits -system.cpu1.dtb.read_misses 72039 # DTB read misses -system.cpu1.dtb.write_hits 71761800 # DTB write hits -system.cpu1.dtb.write_misses 27113 # DTB write misses +system.cpu1.dtb.read_hits 80227147 # DTB read hits +system.cpu1.dtb.read_misses 76874 # DTB read misses +system.cpu1.dtb.write_hits 72873093 # DTB write hits +system.cpu1.dtb.write_misses 28277 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78957050 # DTB read accesses -system.cpu1.dtb.write_accesses 71788913 # DTB write accesses +system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80304021 # DTB read accesses +system.cpu1.dtb.write_accesses 72901370 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 150646811 # DTB hits -system.cpu1.dtb.misses 99152 # DTB misses -system.cpu1.dtb.accesses 150745963 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 153100240 # DTB hits +system.cpu1.dtb.misses 105151 # DTB misses +system.cpu1.dtb.accesses 153205391 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1533,763 +1513,763 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58316 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60537 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 416140593 # ITB inst hits -system.cpu1.itb.inst_misses 58316 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 423099313 # ITB inst hits +system.cpu1.itb.inst_misses 60537 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses -system.cpu1.itb.hits 416140593 # DTB hits -system.cpu1.itb.misses 58316 # DTB misses -system.cpu1.itb.accesses 416198909 # DTB accesses -system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses +system.cpu1.itb.hits 423099313 # DTB hits +system.cpu1.itb.misses 60537 # DTB misses +system.cpu1.itb.accesses 423159850 # DTB accesses +system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94810025921 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94810161765 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed -system.cpu1.committedInsts 415840875 # Number of instructions committed -system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses -system.cpu1.num_func_calls 24835210 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls -system.cpu1.num_int_insts 450775425 # number of integer instructions -system.cpu1.num_fp_insts 467875 # number of float instructions -system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read -system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written -system.cpu1.num_mem_refs 150638767 # number of memory refs -system.cpu1.num_load_insts 78882725 # Number of load instructions -system.cpu1.num_store_insts 71756042 # Number of store instructions -system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles -system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles -system.cpu1.Branches 92635099 # Number of branches fetched +system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed +system.cpu1.committedInsts 422818462 # Number of instructions committed +system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses +system.cpu1.num_func_calls 25225246 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls +system.cpu1.num_int_insts 458669371 # number of integer instructions +system.cpu1.num_fp_insts 488965 # number of float instructions +system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read +system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written +system.cpu1.num_mem_refs 153090665 # number of memory refs +system.cpu1.num_load_insts 80223644 # Number of load instructions +system.cpu1.num_store_insts 72867021 # Number of store instructions +system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles +system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles +system.cpu1.Branches 94103649 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction -system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 8 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 13 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 21 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMisc 67037 0.01% 69.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 78824615 16.07% 85.36% # Class of executed instruction -system.cpu1.op_class::MemWrite 71413356 14.56% 99.92% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 58110 0.01% 99.93% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 342686 0.07% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction +system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 490635753 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4949273 # number of replacements -system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy +system.cpu1.op_class::total 499098010 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5131141 # number of replacements +system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits -system.cpu1.dcache.overall_hits::total 141833557 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses -system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits +system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses +system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks -system.cpu1.dcache.writebacks::total 4949273 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks +system.cpu1.dcache.writebacks::total 5131141 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4981311 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5003710 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits -system.cpu1.icache.overall_hits::total 411158765 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses -system.cpu1.icache.overall_misses::total 4981828 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits +system.cpu1.icache.overall_hits::total 418095086 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses +system.cpu1.icache.overall_misses::total 5004227 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4981311 # number of writebacks -system.cpu1.icache.writebacks::total 4981311 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4981828 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4981828 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4981828 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4981828 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4981828 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4981828 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks +system.cpu1.icache.writebacks::total 5003710 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1861043 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1888854 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 342605185 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 342605185 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 220532 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 147847 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 368379 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3122709 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3122709 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6807120 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6807120 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 835381 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 835381 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4529100 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4529100 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2623579 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2623579 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191618 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 191618 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 220532 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 147847 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4529100 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3458960 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8356439 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 220532 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 147847 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4529100 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3458960 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8356439 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17957 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10279 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 28236 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208369 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 208369 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202239 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 202239 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 250965 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 250965 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 452728 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 452728 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 889177 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 889177 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 249433 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 249433 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17957 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10279 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 452728 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1140142 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1621106 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17957 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10279 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 452728 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1140142 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1621106 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 590137500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 422641500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1012779000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 875652500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 875652500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 333590500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 333590500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2035999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2035999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11238175000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11238175000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16933068500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16933068500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31773824000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31773824000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 403814500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 403814500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 590137500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 422641500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16933068500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43011999000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 60957846500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 590137500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 422641500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16933068500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43011999000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 60957846500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 238489 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 158126 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 396615 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3122709 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3122709 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6807120 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6807120 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208369 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 208369 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202239 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 202239 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1086346 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1086346 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4981828 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 4981828 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3512756 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3512756 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441051 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 441051 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 238489 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 158126 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4981828 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4599102 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 9977545 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 238489 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 158126 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4981828 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4599102 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 9977545 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065005 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.071192 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231018 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231018 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090876 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090876 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253128 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253128 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565542 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565542 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065005 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090876 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247905 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.162475 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065005 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090876 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247905 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.162475 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4202.412547 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4202.412547 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1649.486499 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1649.486499 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1618.929733 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1618.929733 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 38928 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1071108 # number of writebacks -system.cpu1.l2cache.writebacks::total 1071108 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4423 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 4423 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 417 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 417 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4840 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 4840 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4840 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 4840 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17957 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10279 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 28236 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 666851 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208369 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208369 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202239 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202239 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 246542 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 246542 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 452728 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 452728 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 888760 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 888760 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 249433 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 249433 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17957 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10279 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 452728 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135302 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1616266 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17957 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10279 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 452728 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135302 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2283117 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks +system.cpu1.l2cache.writebacks::total 1086447 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22313 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43068 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 360967500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 843363000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27800562984 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3852073000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3852073000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2298,129 +2278,128 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40355 # Transaction distribution -system.iobus.trans_dist::ReadResp 40355 # Transaction distribution -system.iobus.trans_dist::WriteReq 136628 # Transaction distribution -system.iobus.trans_dist::WriteResp 136628 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40383 # Transaction distribution +system.iobus.trans_dist::ReadResp 40383 # Transaction distribution +system.iobus.trans_dist::WriteReq 136636 # Transaction distribution +system.iobus.trans_dist::WriteResp 136636 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2431,15 +2410,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2450,105 +2429,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115615 # number of replacements -system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115614 # number of replacements +system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040856 # Number of tag accesses -system.iocache.tags.data_accesses 1040856 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041054 # Number of tag accesses +system.iocache.tags.data_accesses 1041054 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses -system.iocache.demand_misses::total 115651 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses +system.iocache.demand_misses::total 115673 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115611 # number of overall misses -system.iocache.overall_misses::total 115651 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115633 # number of overall misses +system.iocache.overall_misses::total 115673 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2562,53 +2541,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3343500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8000796585 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8000796585 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3562500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9385295588 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9388858088 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3562500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9385295588 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9388858088 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2622,659 +2601,654 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1376932 # number of replacements -system.l2c.tags.tagsinuse 65061.419917 # Cycle average of tags in use -system.l2c.tags.total_refs 5975056 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1437120 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.157660 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9858759500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11843.449139 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 304.799159 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 356.696004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3585.763677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 19085.445505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1381741 # number of replacements +system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use +system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 68586261 # Number of tag accesses -system.l2c.tags.data_accesses 68586261 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2589224 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2589224 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 191644 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 164185 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 355829 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 48914 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 48173 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 97087 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106304 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 9201 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3860 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 408160 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 537157 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 271610 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10477 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5555 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 408048 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 521656 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 272486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2448210 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 124551 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 127410 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 251961 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 408160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 584894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 271610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 408048 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 580223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 272486 # number of demand (read+write) hits -system.l2c.demand_hits::total 2554514 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9201 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3860 # number of overall hits -system.l2c.overall_hits::cpu0.inst 408160 # number of overall hits -system.l2c.overall_hits::cpu0.data 584894 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 271610 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10477 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5555 # number of overall hits -system.l2c.overall_hits::cpu1.inst 408048 # number of overall hits -system.l2c.overall_hits::cpu1.data 580223 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 272486 # number of overall hits -system.l2c.overall_hits::total 2554514 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 24439 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23204 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 47643 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 628 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 554 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1182 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75730 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50449 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 126179 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1744 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 48585 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 141383 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1973 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 44680 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 100605 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 753125 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 440725 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 106525 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 547250 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1681 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 48585 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 217113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1909 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1973 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 44680 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 151054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) misses -system.l2c.demand_misses::total 879304 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1681 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1744 # number of overall misses -system.l2c.overall_misses::cpu0.inst 48585 # number of overall misses -system.l2c.overall_misses::cpu0.data 217113 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 241091 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1909 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1973 # number of overall misses -system.l2c.overall_misses::cpu1.inst 44680 # number of overall misses -system.l2c.overall_misses::cpu1.data 151054 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 169474 # number of overall misses -system.l2c.overall_misses::total 879304 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 162640000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 138377500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 301017500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7502500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7047000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 14549500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8218459999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5520286999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13738746998 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 167721500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180518500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5556413500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15487743000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 194137000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 210753000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5171670000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 11743795000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 93664269011 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 42596000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 33301500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 75897500 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 167721500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 180518500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5556413500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23706202999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 194137000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 210753000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 5171670000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 17264081999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 107403016009 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 167721500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 180518500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5556413500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23706202999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 194137000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 210753000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 5171670000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 17264081999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of overall miss cycles -system.l2c.overall_miss_latency::total 107403016009 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2589224 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2589224 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 216083 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 187389 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 403472 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 49542 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 48727 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 98269 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123467 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 109016 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 232483 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10882 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5604 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 456745 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 678540 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 512701 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12386 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7528 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 452728 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 622261 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 441960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3201335 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 565276 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 233935 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 799211 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10882 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5604 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 456745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 802007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 512701 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12386 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 452728 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 731277 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 441960 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3433818 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10882 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5604 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 456745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 802007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 512701 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12386 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 452728 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 731277 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 441960 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3433818 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.113100 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.123828 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.118083 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012676 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011369 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.012028 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.613362 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.462767 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.542745 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311206 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106372 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.208364 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.262088 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098691 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.161677 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.235253 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779663 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.455362 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.684738 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.311206 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.106372 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.270712 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.262088 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.098691 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.256072 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.311206 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.106372 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.270712 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.262088 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.098691 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.256072 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6654.936781 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5963.519221 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6318.189451 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 108882.991607 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 96.649838 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 312.616757 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 138.688899 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 122145.487805 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122145.487805 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 340 # number of cycles access was blocked +system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 67794643 # Number of tag accesses +system.l2c.tags.data_accesses 67794643 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits +system.l2c.demand_hits::total 2537328 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits +system.l2c.overall_hits::cpu0.inst 389694 # number of overall hits +system.l2c.overall_hits::cpu0.data 556846 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits +system.l2c.overall_hits::cpu1.inst 424247 # number of overall hits +system.l2c.overall_hits::cpu1.data 597655 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits +system.l2c.overall_hits::total 2537328 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses +system.l2c.demand_misses::total 879096 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses +system.l2c.overall_misses::cpu0.inst 53195 # number of overall misses +system.l2c.overall_misses::cpu0.data 218373 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses +system.l2c.overall_misses::cpu1.inst 39604 # number of overall misses +system.l2c.overall_misses::cpu1.data 151830 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses +system.l2c.overall_misses::total 879096 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles +system.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 16 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 21.250000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1062552 # number of writebacks -system.l2c.writebacks::total 1062552 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 178 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 32 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 57 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 390 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 178 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 32 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 178 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 390 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 55381 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 55381 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 24439 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 23204 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 47643 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 628 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 554 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1182 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 75730 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 50449 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 126179 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1744 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48407 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 141351 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1973 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44557 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 100548 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 752735 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 440725 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 106525 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 547250 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1681 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1744 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 48407 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 217081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1909 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1973 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 44557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 150997 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 878914 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1681 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1744 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 48407 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 217081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1909 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1973 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 44557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 150997 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 878914 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1061178 # number of writebacks +system.l2c.writebacks::total 1061178 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22201 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 81817 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38449 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 42956 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 120266 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 494587500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479394000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 973981500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15163500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13789000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 28952500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7461135548 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5015765562 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 12476901110 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163078500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5057062528 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14070826165 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 191021503 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4714685544 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10733108269 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 86101249279 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8759971500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2141412000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 10901383500 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163078500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5057062528 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21531961713 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191021503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4714685544 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 15748873831 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 98578150389 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 163078500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5057062528 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21531961713 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191021503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4714685544 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 15748873831 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 98578150389 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 12432086139 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 140574501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5355219542 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14279847185 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 196268502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4312153532 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21714443231 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 196268502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 4312153532 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 15765200265 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 98637178589 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2614209002 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7665500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3345576000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8984296502 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4911881502 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 8111000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1045413500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8982252002 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2614209002 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7665500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3345576000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 8984296502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81817 # Transaction distribution -system.membus.trans_dist::ReadResp 843472 # Transaction distribution -system.membus.trans_dist::WriteReq 38449 # Transaction distribution -system.membus.trans_dist::WriteResp 38449 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution -system.membus.trans_dist::CleanEvict 223620 # Transaction distribution -system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 143723 # Transaction distribution -system.membus.trans_dist::ReadExResp 125482 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution -system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81785 # Transaction distribution +system.membus.trans_dist::ReadResp 843578 # Transaction distribution +system.membus.trans_dist::WriteReq 38414 # Transaction distribution +system.membus.trans_dist::WriteResp 38414 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution +system.membus.trans_dist::CleanEvict 225685 # Transaction distribution +system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 142258 # Transaction distribution +system.membus.trans_dist::ReadExResp 125306 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution +system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution +system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 595046 # Total snoops (count) -system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2303059 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 601899 # Total snoops (count) +system.membus.snoopTraffic 182272 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2241138 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram -system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram +system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2303059 # Request fanout histogram -system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2241138 # Request fanout histogram +system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3317,78 +3291,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2818319 # Total snoops (count) -system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2851175 # Total snoops (count) +system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index c8de2f883..9261f2548 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821889 # Number of seconds simulated -sim_ticks 51821888787500 # Number of ticks simulated -final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821872 # Number of seconds simulated +sim_ticks 51821872017500 # Number of ticks simulated +final_tick 51821872017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1225071 # Simulator instruction rate (inst/s) -host_op_rate 1439562 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73854998542 # Simulator tick rate (ticks/s) -host_mem_usage 679352 # Number of bytes of host memory used -host_seconds 701.67 # Real time elapsed on the host -sim_insts 859596485 # Number of instructions simulated -sim_ops 1010098639 # Number of ops (including micro ops) simulated +host_inst_rate 1130306 # Simulator instruction rate (inst/s) +host_op_rate 1328204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68135685678 # Simulator tick rate (ticks/s) +host_mem_usage 679252 # Number of bytes of host memory used +host_seconds 760.57 # Real time elapsed on the host +sim_insts 859675526 # Number of instructions simulated +sim_ops 1010190283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 216448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 219200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5035380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 42867656 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 394432 # Number of bytes read from this memory -system.physmem.bytes_read::total 48733116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5035380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5035380 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69868992 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 215360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 217216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5027508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42852104 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 396352 # Number of bytes read from this memory +system.physmem.bytes_read::total 48708540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5027508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5027508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69916032 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69889572 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3382 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3425 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 119085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 669820 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 801875 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1091703 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69936612 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 669577 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6193 # Number of read requests responded to by this memory +system.physmem.num_reads::total 801491 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1092438 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1094276 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 97167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 827211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 940396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 97167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 97167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1348253 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1095011 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 97015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 826912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 939922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 97015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 97015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1349161 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1348650 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1348253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 97167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 827609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2289046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 801875 # Number of read requests accepted -system.physmem.writeReqs 1094276 # Number of write requests accepted -system.physmem.readBursts 801875 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1094276 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 51277952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 42048 # Total number of bytes read from write queue -system.physmem.bytesWritten 69886912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48733116 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69889572 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 657 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2265 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1349558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1349161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 97015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 827309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2289480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 801491 # Number of read requests accepted +system.physmem.writeReqs 1095011 # Number of write requests accepted +system.physmem.readBursts 801491 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1095011 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 51258176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37248 # Total number of bytes read from write queue +system.physmem.bytesWritten 69934720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48708540 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69936612 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 582 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50164 # Per bank write bursts -system.physmem.perBankRdBursts::1 52640 # Per bank write bursts -system.physmem.perBankRdBursts::2 46199 # Per bank write bursts -system.physmem.perBankRdBursts::3 47700 # Per bank write bursts -system.physmem.perBankRdBursts::4 47678 # Per bank write bursts -system.physmem.perBankRdBursts::5 54947 # Per bank write bursts -system.physmem.perBankRdBursts::6 45482 # Per bank write bursts -system.physmem.perBankRdBursts::7 44174 # Per bank write bursts -system.physmem.perBankRdBursts::8 47146 # Per bank write bursts -system.physmem.perBankRdBursts::9 89983 # Per bank write bursts -system.physmem.perBankRdBursts::10 47048 # Per bank write bursts -system.physmem.perBankRdBursts::11 49101 # Per bank write bursts -system.physmem.perBankRdBursts::12 43837 # Per bank write bursts -system.physmem.perBankRdBursts::13 45399 # Per bank write bursts -system.physmem.perBankRdBursts::14 43891 # Per bank write bursts -system.physmem.perBankRdBursts::15 45829 # Per bank write bursts -system.physmem.perBankWrBursts::0 68109 # Per bank write bursts -system.physmem.perBankWrBursts::1 72083 # Per bank write bursts -system.physmem.perBankWrBursts::2 69263 # Per bank write bursts -system.physmem.perBankWrBursts::3 69948 # Per bank write bursts -system.physmem.perBankWrBursts::4 67942 # Per bank write bursts -system.physmem.perBankWrBursts::5 73995 # Per bank write bursts -system.physmem.perBankWrBursts::6 66206 # Per bank write bursts -system.physmem.perBankWrBursts::7 65273 # Per bank write bursts -system.physmem.perBankWrBursts::8 68509 # Per bank write bursts -system.physmem.perBankWrBursts::9 70672 # Per bank write bursts -system.physmem.perBankWrBursts::10 68078 # Per bank write bursts -system.physmem.perBankWrBursts::11 68626 # Per bank write bursts -system.physmem.perBankWrBursts::12 64922 # Per bank write bursts -system.physmem.perBankWrBursts::13 66812 # Per bank write bursts -system.physmem.perBankWrBursts::14 65438 # Per bank write bursts -system.physmem.perBankWrBursts::15 66107 # Per bank write bursts +system.physmem.perBankRdBursts::0 50792 # Per bank write bursts +system.physmem.perBankRdBursts::1 52585 # Per bank write bursts +system.physmem.perBankRdBursts::2 45494 # Per bank write bursts +system.physmem.perBankRdBursts::3 47583 # Per bank write bursts +system.physmem.perBankRdBursts::4 47505 # Per bank write bursts +system.physmem.perBankRdBursts::5 55338 # Per bank write bursts +system.physmem.perBankRdBursts::6 45272 # Per bank write bursts +system.physmem.perBankRdBursts::7 44194 # Per bank write bursts +system.physmem.perBankRdBursts::8 47329 # Per bank write bursts +system.physmem.perBankRdBursts::9 89850 # Per bank write bursts +system.physmem.perBankRdBursts::10 47381 # Per bank write bursts +system.physmem.perBankRdBursts::11 49509 # Per bank write bursts +system.physmem.perBankRdBursts::12 42888 # Per bank write bursts +system.physmem.perBankRdBursts::13 45239 # Per bank write bursts +system.physmem.perBankRdBursts::14 44185 # Per bank write bursts +system.physmem.perBankRdBursts::15 45765 # Per bank write bursts +system.physmem.perBankWrBursts::0 68303 # Per bank write bursts +system.physmem.perBankWrBursts::1 72266 # Per bank write bursts +system.physmem.perBankWrBursts::2 69005 # Per bank write bursts +system.physmem.perBankWrBursts::3 70230 # Per bank write bursts +system.physmem.perBankWrBursts::4 67390 # Per bank write bursts +system.physmem.perBankWrBursts::5 74059 # Per bank write bursts +system.physmem.perBankWrBursts::6 66126 # Per bank write bursts +system.physmem.perBankWrBursts::7 65521 # Per bank write bursts +system.physmem.perBankWrBursts::8 69259 # Per bank write bursts +system.physmem.perBankWrBursts::9 70740 # Per bank write bursts +system.physmem.perBankWrBursts::10 68902 # Per bank write bursts +system.physmem.perBankWrBursts::11 68447 # Per bank write bursts +system.physmem.perBankWrBursts::12 64485 # Per bank write bursts +system.physmem.perBankWrBursts::13 66687 # Per bank write bursts +system.physmem.perBankWrBursts::14 65337 # Per bank write bursts +system.physmem.perBankWrBursts::15 65973 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 528 # Number of times write queue was full causing retry -system.physmem.totGap 51821885925500 # Total gap between requests +system.physmem.numWrRetry 520 # Number of times write queue was full causing retry +system.physmem.totGap 51821869155500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 758759 # Read request sizes (log2) +system.physmem.readPktSize::6 758375 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1091703 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 767795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1092438 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 767476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,129 +161,129 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 64819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 65819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 58775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1157 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 494449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.049629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.402723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.016754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 219085 44.31% 44.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 131738 26.64% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43693 8.84% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22796 4.61% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15362 3.11% 87.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9595 1.94% 89.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7428 1.50% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5929 1.20% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38823 7.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 494449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.008130 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 134.294281 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57192 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 64813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 66047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 58755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1058 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 494423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.119212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.459226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.994040 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 219027 44.30% 44.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 131709 26.64% 70.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43564 8.81% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22937 4.64% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15466 3.13% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9602 1.94% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7396 1.50% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5862 1.19% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38860 7.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 494423 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.013543 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 134.391751 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57148 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57195 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.092281 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.359425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.356307 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 44576 77.94% 77.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9441 16.51% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 730 1.28% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 284 0.50% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 871 1.52% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 293 0.51% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 0.08% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.06% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.03% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.03% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.02% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 33 0.06% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 518 0.91% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 69 0.12% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 50 0.09% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 58 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 36 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 17 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 57152 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.119716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.362666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.513001 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 44632 78.09% 78.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9484 16.59% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 590 1.03% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 287 0.50% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 876 1.53% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 130 0.23% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 0.19% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 28 0.05% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 52 0.09% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.03% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.03% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 48 0.08% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 542 0.95% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 77 0.13% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 52 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 79 0.14% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 35 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 6 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57195 # Writes before turning the bus around for reads -system.physmem.totQLat 29399013585 # Total ticks spent queuing -system.physmem.totMemAccLat 44421851085 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4006090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36692.90 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57152 # Writes before turning the bus around for reads +system.physmem.totQLat 29342800943 # Total ticks spent queuing +system.physmem.totMemAccLat 44359844693 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4004545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36636.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55442.90 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 55386.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s @@ -293,52 +293,52 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 600273 # Number of row buffer hits during reads -system.physmem.writeRowHits 798478 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.92 # Row buffer hit rate for reads +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 600164 # Number of row buffer hits during reads +system.physmem.writeRowHits 799051 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes -system.physmem.avgGap 27330041.71 # Average gap between requests -system.physmem.pageHitRate 73.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1812881700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 963565680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2777345760 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2885715180 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 48801801360.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38319920670 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3025839840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94040362440 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 72590911200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12330316288695 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12595556394525 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.054753 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51729925726993 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5744734750 # Time in different power states -system.physmem_0.memoryStateTime::REF 20754236000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51334657894500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 189038733198 # Time in different power states -system.physmem_0.memoryStateTime::ACT 65464048007 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 206229141045 # Time in different power states -system.physmem_1.actEnergy 1717491300 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 912868275 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2943350760 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2814436080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 46544843280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 38176673400 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2758502400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 87988375470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 69794301120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12334956932460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12588629106345 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.921078 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51730316233255 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5091528742 # Time in different power states -system.physmem_1.memoryStateTime::REF 19793960000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51356223942250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 181755962683 # Time in different power states -system.physmem_1.memoryStateTime::ACT 66066776003 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 192956617822 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.physmem.avgGap 27324974.69 # Average gap between requests +system.physmem.pageHitRate 73.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1814238300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 964290525 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2775767820 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2886138000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 48823313760.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 38608999590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3011693280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94024683450 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 72592857120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12330153384360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12595677850665 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.057176 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51728729641480 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5702683750 # Time in different power states +system.physmem_0.memoryStateTime::REF 20763204000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51334071775500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 189043780464 # Time in different power states +system.physmem_0.memoryStateTime::ACT 66096536270 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 206194037516 # Time in different power states +system.physmem_1.actEnergy 1715949060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 912044760 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2942722440 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2817912600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 46334636400.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 38117726280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2754271680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 87558235230 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 69416939040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12335402832360 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12587993852010 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.908898 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51731061753764 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5083631742 # Time in different power states +system.physmem_1.memoryStateTime::REF 19704542000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51358275119250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 180773350699 # Time in different power states +system.physmem_1.memoryStateTime::ACT 66022048244 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 192013325565 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -355,9 +355,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -365,7 +365,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,74 +395,75 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 195978 # Table walker walks requested -system.cpu.dtb.walker.walksLong 195978 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13491 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152311 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 195958 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.153094 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 48.869782 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 195956 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 196189 # Table walker walks requested +system.cpu.dtb.walker.walksLong 196189 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13637 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152377 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 196170 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.152929 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 48.843369 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 196168 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 195958 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 165822 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 164137 98.98% 98.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1390 0.84% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 75 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 54 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 79 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 196170 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 166033 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 164361 98.99% 98.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1402 0.84% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 64 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 64 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 59 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 17 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 53 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 165822 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -2782551036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.846086 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.360866 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -428273296 15.39% 15.39% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -2354277740 84.61% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -2782551036 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 152312 91.86% 91.86% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 13491 8.14% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 165803 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 195978 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::589824-655359 48 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 166033 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -7075428332 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.933158 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.249747 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -472932796 6.68% 6.68% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -6602495536 93.32% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -7075428332 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 152378 91.79% 91.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 13637 8.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 166015 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 196189 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 195978 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 165803 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 196189 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 166015 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 165803 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 361781 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 166015 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 362204 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 161602593 # DTB read hits -system.cpu.dtb.read_misses 145506 # DTB read misses -system.cpu.dtb.write_hits 146806893 # DTB write hits -system.cpu.dtb.write_misses 50472 # DTB write misses +system.cpu.dtb.read_hits 161617169 # DTB read hits +system.cpu.dtb.read_misses 145721 # DTB read misses +system.cpu.dtb.write_hits 146821389 # DTB write hits +system.cpu.dtb.write_misses 50468 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72949 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 72934 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7287 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7326 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 161748099 # DTB read accesses -system.cpu.dtb.write_accesses 146857365 # DTB write accesses +system.cpu.dtb.read_accesses 161762890 # DTB read accesses +system.cpu.dtb.write_accesses 146871857 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 308409486 # DTB hits -system.cpu.dtb.misses 195978 # DTB misses -system.cpu.dtb.accesses 308605464 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 308438558 # DTB hits +system.cpu.dtb.misses 196189 # DTB misses +system.cpu.dtb.accesses 308634747 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -492,43 +493,46 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 120718 # Table walker walks requested -system.cpu.itb.walker.walksLong 120718 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 120716 # Table walker walks requested +system.cpu.itb.walker.walksLong 120716 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 108838 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 120718 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 120718 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 120718 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 109957 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27485.576180 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107960 98.18% 98.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1664 1.51% 99.70% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 68 0.06% 99.76% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 86 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 74 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 76 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 109957 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 108836 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 120716 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 120716 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 120716 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 109955 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27513.978446 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107988 98.21% 98.21% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1629 1.48% 99.69% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 80 0.07% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 85 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 60 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 77 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 109955 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 108838 98.98% 98.98% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 108836 98.98% 98.98% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 109957 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 109955 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120718 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 120718 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120716 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 120716 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 109957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 230675 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 860126625 # ITB inst hits -system.cpu.itb.inst_misses 120718 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 109955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 230671 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 860205714 # ITB inst hits +system.cpu.itb.inst_misses 120716 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -537,22 +541,22 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52157 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52133 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 860247343 # ITB inst accesses -system.cpu.itb.hits 860126625 # DTB hits -system.cpu.itb.misses 120718 # DTB misses -system.cpu.itb.accesses 860247343 # DTB accesses -system.cpu.numPwrStateTransitions 32322 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16161 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3111677574.020791 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60407510991.245888 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6870 42.51% 42.51% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 860326430 # ITB inst accesses +system.cpu.itb.hits 860205714 # DTB hits +system.cpu.itb.misses 120716 # DTB misses +system.cpu.itb.accesses 860326430 # DTB accesses +system.cpu.numPwrStateTransitions 32324 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3111484469.414615 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60405660268.224297 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6871 42.51% 42.51% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state @@ -566,40 +570,40 @@ system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16161 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1534067513750 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103643777575 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 16162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1534060022821 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103643744035 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16161 # number of quiesce instructions executed -system.cpu.committedInsts 859596485 # Number of instructions committed -system.cpu.committedOps 1010098639 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 927989339 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 896850 # Number of float alu accesses -system.cpu.num_func_calls 51273640 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 130821573 # number of instructions that are conditional controls -system.cpu.num_int_insts 927989339 # number of integer instructions -system.cpu.num_fp_insts 896850 # number of float instructions -system.cpu.num_int_register_reads 1348541336 # number of times the integer registers were read -system.cpu.num_int_register_writes 735865236 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1446705 # number of times the floating registers were read -system.cpu.num_fp_register_writes 758956 # number of times the floating registers were written -system.cpu.num_cc_register_reads 224361660 # number of times the CC registers were read -system.cpu.num_cc_register_writes 223761478 # number of times the CC registers were written -system.cpu.num_mem_refs 308390268 # number of memory refs -system.cpu.num_load_insts 161593947 # Number of load instructions -system.cpu.num_store_insts 146796321 # Number of store instructions -system.cpu.num_idle_cycles 100575642547.498062 # Number of idle cycles -system.cpu.num_busy_cycles 3068135027.501941 # Number of busy cycles +system.cpu.kern.inst.quiesce 16162 # number of quiesce instructions executed +system.cpu.committedInsts 859675526 # Number of instructions committed +system.cpu.committedOps 1010190283 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 928076114 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 896946 # Number of float alu accesses +system.cpu.num_func_calls 51280324 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 130830869 # number of instructions that are conditional controls +system.cpu.num_int_insts 928076114 # number of integer instructions +system.cpu.num_fp_insts 896946 # number of float instructions +system.cpu.num_int_register_reads 1348653813 # number of times the integer registers were read +system.cpu.num_int_register_writes 735932841 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1446833 # number of times the floating registers were read +system.cpu.num_fp_register_writes 759084 # number of times the floating registers were written +system.cpu.num_cc_register_reads 224374440 # number of times the CC registers were read +system.cpu.num_cc_register_writes 223774216 # number of times the CC registers were written +system.cpu.num_mem_refs 308419372 # number of memory refs +system.cpu.num_load_insts 161608555 # Number of load instructions +system.cpu.num_store_insts 146810817 # Number of store instructions +system.cpu.num_idle_cycles 100575623989.356064 # Number of idle cycles +system.cpu.num_busy_cycles 3068120045.643941 # Number of busy cycles system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles system.cpu.idle_fraction 0.970397 # Percentage of idle cycles -system.cpu.Branches 191892206 # Number of branches fetched +system.cpu.Branches 191908708 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction -system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction -system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction +system.cpu.op_class::IntAlu 699966855 69.25% 69.25% # Class of executed instruction +system.cpu.op_class::IntMult 2168337 0.21% 69.47% # Class of executed instruction +system.cpu.op_class::IntDiv 97451 0.01% 69.48% # Class of executed instruction system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction @@ -628,539 +632,535 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::MemRead 161481542 15.98% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 146123455 14.46% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemRead 112405 0.01% 99.93% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 672866 0.07% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 161496118 15.98% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 146137887 14.46% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112437 0.01% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 672930 0.07% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1010671903 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9712865 # number of replacements +system.cpu.op_class::total 1010763595 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9712819 # number of replacements system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 298498000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9713377 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.730610 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 298526964 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9713331 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.733737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243014374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243014374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 151150245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 151150245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 139360023 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 139360023 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 383359 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 383359 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333234 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333234 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475622 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3475622 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3766718 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3766718 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 290843502 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 290843502 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 291226861 # number of overall hits -system.cpu.dcache.overall_hits::total 291226861 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5063029 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5063029 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2070213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2070213 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1203887 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1203887 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1226147 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1226147 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 292765 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 292765 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1243130616 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1243130616 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 151166129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 151166129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 139372457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 139372457 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 383388 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 383388 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 333792 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 333792 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475542 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3475542 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3766859 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3766859 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 290872378 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 290872378 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 291255766 # number of overall hits +system.cpu.dcache.overall_hits::total 291255766 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5061632 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5061632 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2072136 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2072136 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1203806 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1203806 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1225587 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1225587 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 292986 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 292986 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8359389 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8359389 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9563276 # number of overall misses -system.cpu.dcache.overall_misses::total 9563276 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 86479051000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 86479051000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64029512000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64029512000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24965286000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 24965286000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4461300000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4461300000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 8359355 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8359355 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9563161 # number of overall misses +system.cpu.dcache.overall_misses::total 9563161 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 86410296000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 86410296000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64078644000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64078644000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24971401500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 24971401500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4471115500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4471115500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 175473849000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 175473849000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 175473849000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 175473849000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156213274 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156213274 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141430236 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141430236 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587246 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1587246 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559381 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1559381 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768387 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3768387 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766720 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3766720 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299202891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299202891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300790137 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300790137 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032411 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032411 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014638 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014638 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758475 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758475 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786304 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786304 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077690 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 175460341500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 175460341500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 175460341500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 175460341500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156227761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156227761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 141444593 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 141444593 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587194 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1587194 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559379 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1559379 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3768528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766861 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3766861 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299231733 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299231733 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300818927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300818927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032399 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032399 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014650 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758449 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758449 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785946 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785946 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077745 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077745 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027939 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027939 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031794 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031794 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.027936 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027936 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031790 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031790 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20991.229024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18348.717427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20989.698547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18347.525625 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7498102 # number of writebacks -system.cpu.dcache.writebacks::total 7498102 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21612 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21612 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21289 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21289 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70591 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70591 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 42901 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 42901 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 42901 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 42901 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5041417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5041417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2048924 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2048924 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203533 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1203533 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226147 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226147 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222174 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 222174 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 7496626 # number of writebacks +system.cpu.dcache.writebacks::total 7496626 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21661 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21294 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70691 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70691 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 42955 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 42955 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 42955 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 42955 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5039971 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5039971 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2050842 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2050842 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203452 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1203452 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1225587 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1225587 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222295 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 222295 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8316488 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8316488 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9520021 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9520021 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8316400 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8316400 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9519852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9519852 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80551413000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80551413000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61232027000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61232027000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21569596000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21569596000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23739139000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23739139000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3061958500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3061958500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80495651000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 80495651000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61277537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61277537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21572116000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21572116000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23745814500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23745814500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3066936500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3066936500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165522579000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187092175000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032273 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032273 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014487 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014487 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758252 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758252 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786304 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786304 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058957 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058957 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165519002500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187091118500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032260 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032260 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014499 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014499 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758226 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758226 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785946 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785946 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058987 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058987 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031650 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031646 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031646 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13489644 # number of replacements +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13486266 # number of replacements system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 846636464 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13490156 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62.759576 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32464202500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 846718931 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13486778 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62.781409 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32464203500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 873616786 # Number of tag accesses -system.cpu.icache.tags.data_accesses 873616786 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 846636464 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 846636464 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 846636464 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 846636464 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 846636464 # number of overall hits -system.cpu.icache.overall_hits::total 846636464 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13490161 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13490161 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13490161 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13490161 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13490161 # number of overall misses -system.cpu.icache.overall_misses::total 13490161 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 183617881000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 183617881000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 183617881000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 183617881000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 183617881000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 860126625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 860126625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 860126625 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 860126625 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 860126625 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 860126625 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015684 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015684 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015684 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015684 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015684 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13611.244595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13611.244595 # average overall miss latency +system.cpu.icache.tags.tag_accesses 873692497 # Number of tag accesses +system.cpu.icache.tags.data_accesses 873692497 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 846718931 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 846718931 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 846718931 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 846718931 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 846718931 # number of overall hits +system.cpu.icache.overall_hits::total 846718931 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13486783 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13486783 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13486783 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13486783 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13486783 # number of overall misses +system.cpu.icache.overall_misses::total 13486783 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 183511474500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 183511474500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 183511474500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 183511474500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 183511474500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 860205714 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 860205714 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 860205714 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 860205714 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 860205714 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 860205714 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015679 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015679 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015679 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015679 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015679 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015679 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13606.764082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13606.764082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13489644 # number of writebacks -system.cpu.icache.writebacks::total 13489644 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13490161 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13490161 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13490161 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13490161 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13490161 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13490161 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 13486266 # number of writebacks +system.cpu.icache.writebacks::total 13486266 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13486783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13486783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13486783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13486783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13486783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13486783 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170127720000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170127720000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170127720000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170024691500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170024691500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015684 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015684 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12611.244595 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12611.244595 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015679 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015679 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015679 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1158676 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65394.159072 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 44435371 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1220446 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 36.409125 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1158711 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65407.211772 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 44429708 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1220523 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 36.402188 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 465.362855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 539.855564 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.163394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46827.778856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.166183 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008238 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.714535 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61492 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5790 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54645 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 377782006 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 377782006 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307317 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 227975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 535292 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7498102 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7498102 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13488047 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13488047 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 24835 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 24835 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1605264 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1605264 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13414164 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 13414164 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6210983 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6210983 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 729246 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 729246 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 307317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 227975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13414164 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7816247 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21765703 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 307317 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 227975 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13414164 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7816247 # number of overall hits -system.cpu.l2cache.overall_hits::total 21765703 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3382 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 6807 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3962 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3962 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 463.658135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 540.023475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6661.801500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.167221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007075 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.713848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61511 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 815 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54668 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938583 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 377726834 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 377726834 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 228330 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 535411 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7496626 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7496626 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13484674 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13484674 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 24887 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 24887 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1607168 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1607168 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13410909 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 13410909 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6209836 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6209836 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 727975 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 727975 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 307081 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 228330 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13410909 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7817004 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 21763324 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 307081 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 228330 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13410909 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7817004 # number of overall hits +system.cpu.l2cache.overall_hits::total 21763324 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3365 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3394 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 6759 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3908 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3908 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 414863 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 414863 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75997 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 75997 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256141 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 256141 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 496901 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 496901 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3382 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3425 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 75997 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 671004 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 753808 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3382 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3425 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 75997 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 671004 # number of overall misses -system.cpu.l2cache.overall_misses::total 753808 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 458444500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 422573500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 881018000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69853000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 69853000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 414879 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 414879 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75874 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 75874 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 255882 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 255882 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 497612 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 497612 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3365 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3394 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 75874 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 670761 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 753394 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3365 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3394 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 75874 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 670761 # number of overall misses +system.cpu.l2cache.overall_misses::total 753394 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 447362000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 421528500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 868890500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69021500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 69021500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40877442000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40877442000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8773195000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 8773195000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30189333000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30189333000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 454500 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 454500 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 458444500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 422573500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8773195000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 71066775000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 80720988000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 458444500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 422573500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8773195000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 71066775000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 80720988000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310699 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231400 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 542099 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7498102 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7498102 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13488047 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13488047 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28797 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 28797 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40901099500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40901099500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8709565500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 8709565500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30155420000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30155420000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 447362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 421528500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8709565500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 71056519500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 80634975500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 447362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 421528500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8709565500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 71056519500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 80634975500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310446 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231724 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 542170 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7496626 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7496626 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13484674 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13484674 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28795 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 28795 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2020127 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2020127 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13490161 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 13490161 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6467124 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 6467124 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226147 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1226147 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310699 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 231400 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13490161 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8487251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 22519511 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310699 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 231400 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13490161 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8487251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 22519511 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010885 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014801 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012557 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.137584 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.137584 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2022047 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2022047 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13486783 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 13486783 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6465718 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6465718 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1225587 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1225587 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310446 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 231724 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13486783 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8487765 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 22516718 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310446 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 231724 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13486783 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8487765 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 22516718 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010839 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014647 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012467 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.135718 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135718 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205365 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.205365 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005634 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005634 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039607 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039607 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.405254 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.405254 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010885 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014801 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005634 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.079060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.033474 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010885 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014801 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005634 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.079060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.033474 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135554.257836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 123379.124088 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 129428.235640 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17630.742049 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17630.742049 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205178 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.205178 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039575 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039575 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.406019 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.406019 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010839 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014647 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.079027 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.033459 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010839 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014647 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.079027 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.033459 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132945.616642 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 124198.143783 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 128553.114366 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17661.591607 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17661.591607 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98532.387800 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98532.387800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115441.333211 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115441.333211 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117862.165760 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117862.165760 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.914669 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.914669 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 107084.281409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 107084.281409 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98585.610503 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98585.610503 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114789.855550 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114789.855550 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117848.930366 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117848.930366 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 107028.958951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 107028.958951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 985073 # number of writebacks -system.cpu.l2cache.writebacks::total 985073 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3382 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3425 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 6807 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3962 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3962 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 985808 # number of writebacks +system.cpu.l2cache.writebacks::total 985808 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3365 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3394 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6759 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3908 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3908 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414863 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 414863 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75997 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75997 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256141 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256141 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 496901 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 496901 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3382 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3425 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 75997 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 671004 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 753808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3382 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3425 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 75997 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 671004 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 753808 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414879 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 414879 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75874 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75874 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 255882 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 255882 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497612 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 497612 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 75874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 670761 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 753394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3365 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 75874 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 670761 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 753394 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable @@ -1169,154 +1169,154 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 424624500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 388323500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 812948000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75436500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75436500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413712000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387588500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 801300500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 74391500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 74391500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36728812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36728812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8013225000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8013225000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27627908030 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27627908030 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9273801000 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9273801000 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 424624500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 388323500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8013225000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64356720030 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 73182893030 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 424624500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 388323500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8013225000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64356720030 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 73182893030 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36752309500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36752309500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7950825500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7950825500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27596583533 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27596583533 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9287554000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9287554000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413712000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387588500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7950825500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64348893033 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 73101019033 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413712000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387588500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7950825500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64348893033 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 73101019033 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828933500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828934000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828933500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012557 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.137584 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.137584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828934000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012467 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135718 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135718 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205365 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205365 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039607 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039607 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405254 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405254 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.033474 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.033474 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119428.235640 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19040.005048 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205178 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205178 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005626 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039575 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039575 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406019 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406019 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033459 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88532.387800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88532.387800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105441.333211 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105441.333211 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107862.107316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107862.107316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18663.276991 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18663.276991 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 46934872 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23731321 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1965 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1965 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 46927036 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23726903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1976 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1976 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1010835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20969000 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1011319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20964705 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8483175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13489644 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2388366 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 28800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8482434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13486266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2389096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28798 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 28802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2020127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2020127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13490161 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6470086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1256693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226147 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40556216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592159 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 883944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 71365293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726880020 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023309382 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1851200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2485592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2754526194 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1584975 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66236232 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25469090 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.139236 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 28800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2022047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2022047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13486783 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6468652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1256381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1225599 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40546082 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332849 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 884181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 71355589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726447636 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023248134 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1853792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2483568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2754033130 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1585660 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66286896 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 25466403 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019742 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.139111 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24965367 98.02% 98.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 503723 1.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24963657 98.03% 98.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 502746 1.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25469090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 44744307000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25466403 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 44736270000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1625890 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1643382 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20278366500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20273299500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13408934951 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13409418464 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 360759000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 360753000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 573245000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 573735000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40342 # Transaction distribution +system.iobus.trans_dist::ReadResp 40342 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1333,11 +1333,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353826 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1352,12 +1352,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492552 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492520 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42151500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1379,75 +1379,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25714500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25717000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569287162 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569022926 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147802000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115506 # number of replacements -system.iocache.tags.tagsinuse 10.457104 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115502 # number of replacements +system.iocache.tags.tagsinuse 10.457099 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115518 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154766855000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510739 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946366 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13154766854000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510741 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946357 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434148 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434147 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040082 # Number of tag accesses -system.iocache.tags.data_accesses 1040082 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040046 # Number of tag accesses +system.iocache.tags.data_accesses 1040046 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses -system.iocache.demand_misses::total 115565 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115521 # number of demand (read+write) misses +system.iocache.demand_misses::total 115561 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115525 # number of overall misses -system.iocache.overall_misses::total 115565 # number of overall misses +system.iocache.overall_misses::realview.ide 115521 # number of overall misses +system.iocache.overall_misses::total 115561 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2019214145 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2024300645 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2023754150 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2028840650 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13409527517 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13409527517 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13483489276 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13483489276 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15428741662 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15434179162 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15507243426 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15512680926 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15428741662 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15434179162 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15507243426 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15512680926 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115521 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115561 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115521 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115561 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1462,52 +1462,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 227500.634412 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 228113.407915 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 133554.096500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134238.029491 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 133554.096500 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51750 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134238.029491 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 52159 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3356 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.420143 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.574500 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115521 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115561 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115521 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115561 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1576164145 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1579400645 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1580904150 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1584140650 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8069228353 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8069228353 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8144739087 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8144739087 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9645392498 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9648829998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9725643237 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9729080737 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9645392498 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9648829998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9725643237 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9729080737 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1522,94 +1522,95 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 2643885 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1308749 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3600 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2644146 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1308848 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 424674 # Transaction distribution +system.membus.trans_dist::ReadResp 424240 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1091703 # Transaction distribution -system.membus.trans_dist::CleanEvict 181416 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1092438 # Transaction distribution +system.membus.trans_dist::CleanEvict 180711 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4469 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 414305 # Transaction distribution -system.membus.trans_dist::ReadExResp 414305 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347843 # Transaction distribution -system.membus.trans_dist::InvalidateReq 603558 # Transaction distribution +system.membus.trans_dist::ReadExReq 414321 # Transaction distribution +system.membus.trans_dist::ReadExResp 414321 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 347409 # Transaction distribution +system.membus.trans_dist::InvalidateReq 604276 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30630 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256260 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3623198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256123 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3623083 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111403936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111573786 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 118792538 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3397 # Total snoops (count) -system.membus.snoopTraffic 216896 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1480779 # Request fanout histogram -system.membus.snoop_fanout::mean 0.023089 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.150185 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111424480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111594330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7220672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 118815002 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 33993 # Total snoops (count) +system.membus.snoopTraffic 214720 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1481018 # Request fanout histogram +system.membus.snoop_fanout::mean 0.023235 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.150648 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1446590 97.69% 97.69% # Request fanout histogram -system.membus.snoop_fanout::1 34189 2.31% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1446607 97.68% 97.68% # Request fanout histogram +system.membus.snoop_fanout::1 34411 2.32% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1480779 # Request fanout histogram -system.membus.reqLayer0.occupancy 106893000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1481018 # Request fanout histogram +system.membus.reqLayer0.occupancy 106898000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5820500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5816000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7180364209 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7183768776 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4203282304 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4201020680 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44877398 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76902808 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1652,28 +1653,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 0c54e3227..bf75cb6d5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62552970500 # Number of ticks simulated -final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 62553193500 # Number of ticks simulated +final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 423901 # Simulator instruction rate (inst/s) -host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292664487 # Simulator tick rate (ticks/s) -host_mem_usage 404124 # Number of bytes of host memory used -host_seconds 213.74 # Real time elapsed on the host +host_inst_rate 434587 # Simulator instruction rate (inst/s) +host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 300043763 # Simulator tick rate (ticks/s) +host_mem_usage 405580 # Number of bytes of host memory used +host_seconds 208.48 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62552869500 # Total gap between requests +system.physmem.totGap 62553092500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # By system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211081250 # Total ticks spent queuing -system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 211075250 # Total ticks spent queuing +system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -221,24 +221,24 @@ system.physmem.readRowHits 14027 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016493.48 # Average gap between requests +system.physmem.avgGap 4016507.80 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612376 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.612326 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states @@ -247,21 +247,21 @@ system.physmem_1.preEnergy 2641320 # En system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503567 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503484 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 20808248 # Number of BP lookups system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect @@ -276,7 +276,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125105941 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125106387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380817 # CPI: cycles per instruction -system.cpu.ipc 0.724209 # IPC: instructions per cycle +system.cpu.cpi 1.380822 # CPI: cycles per instruction +system.cpu.ipc 0.724206 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -465,9 +465,9 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits @@ -476,28 +476,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits -system.cpu.dcache.overall_hits::total 26267138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits +system.cpu.dcache.overall_hits::total 26266955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses -system.cpu.dcache.overall_misses::total 980631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses +system.cpu.dcache.overall_misses::total 980814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -512,24 +512,24 @@ system.cpu.dcache.demand_accesses::cpu.data 27247257 # system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,14 +538,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -556,16 +556,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -576,24 +576,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id @@ -604,7 +604,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740 system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits @@ -617,12 +617,12 @@ system.cpu.icache.demand_misses::cpu.inst 801 # n system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses @@ -635,12 +635,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id @@ -694,7 +694,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -723,18 +723,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -763,18 +763,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,18 +803,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -827,25 +827,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -885,7 +885,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -906,7 +906,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 4f68c8fbf..2da35dc4f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058675 # Number of seconds simulated -sim_ticks 58675371500 # Number of ticks simulated -final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058681 # Number of seconds simulated +sim_ticks 58681066500 # Number of ticks simulated +final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241655 # Simulator instruction rate (inst/s) -host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156520643 # Simulator tick rate (ticks/s) -host_mem_usage 492304 # Number of bytes of host memory used -host_seconds 374.87 # Real time elapsed on the host +host_inst_rate 243006 # Simulator instruction rate (inst/s) +host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157411271 # Simulator tick rate (ticks/s) +host_mem_usage 492224 # Number of bytes of host memory used +host_seconds 372.79 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18533 # Number of read requests accepted -system.physmem.writeReqs 104 # Number of write requests accepted -system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory +system.physmem.bytes_written::total 6784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory +system.physmem.num_writes::total 106 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18543 # Number of read requests accepted +system.physmem.writeReqs 106 # Number of write requests accepted +system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one +system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 3245 # Per bank write bursts system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 952 # Per bank write bursts +system.physmem.perBankRdBursts::2 954 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1118 # Per bank write bursts -system.physmem.perBankRdBursts::6 1097 # Per bank write bursts -system.physmem.perBankRdBursts::7 1096 # Per bank write bursts +system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::6 1093 # Per bank write bursts +system.physmem.perBankRdBursts::7 1100 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 903 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 3 # Per bank write bursts -system.physmem.perBankWrBursts::3 3 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 10 # Per bank write bursts -system.physmem.perBankWrBursts::6 15 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 1 # Per bank write bursts -system.physmem.perBankWrBursts::11 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 5 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 7 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 8 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58675363000 # Total gap between requests +system.physmem.totGap 58681058000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18533 # Read request sizes (log2) +system.physmem.readPktSize::6 18543 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 104 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see +system.physmem.writePktSize::6 106 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -162,7 +162,7 @@ system.physmem.wrQLenPdf::24 5 # Wh system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -198,24 +198,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes @@ -225,82 +225,82 @@ system.physmem.wrPerTurnAround::mean 18 # Wr system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 819558662 # Total ticks spent queuing -system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst +system.physmem.totQLat 829373528 # Total ticks spent queuing +system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing -system.physmem.readRowHits 15523 # Number of row buffer hits during reads -system.physmem.writeRowHits 12 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes -system.physmem.avgGap 3148326.61 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.815504 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states -system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states -system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states -system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.006594 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states -system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states -system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234010 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing +system.physmem.readRowHits 15527 # Number of row buffer hits during reads +system.physmem.writeRowHits 11 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes +system.physmem.avgGap 3146606.15 # Average gap between requests +system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) +system.physmem_0.averagePower 336.871642 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states +system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states +system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) +system.physmem_1.averagePower 255.427603 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states +system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states +system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28234239 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,132 +421,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117350744 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117362134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -571,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued -system.cpu.iq.rate 0.863794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued +system.cpu.iq.rate 0.863706 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621332 # Number of branches executed -system.cpu.iew.exec_stores 4915668 # Number of stores executed -system.cpu.iew.exec_rate 0.853083 # Inst execution rate -system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691499 # num instructions producing a value -system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621210 # Number of branches executed +system.cpu.iew.exec_stores 4915786 # Number of stores executed +system.cpu.iew.exec_rate 0.853001 # Inst execution rate +system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59692176 # num instructions producing a value +system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value +system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +704,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218887121 # The number of ROB reads -system.cpu.rob.rob_writes 219522508 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218899309 # The number of ROB reads +system.cpu.rob.rob_writes 219523661 # The number of ROB writes +system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097860 # number of integer regfile reads -system.cpu.int_regfile_writes 58692141 # number of integer regfile writes +system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads +system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108098001 # number of integer regfile reads +system.cpu.int_regfile_writes 58691976 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads +system.cpu.fp_regfile_writes 98 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470621 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470632 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits -system.cpu.dcache.overall_hits::total 18241616 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits +system.cpu.dcache.overall_hits::total 18242046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses -system.cpu.dcache.overall_misses::total 9968629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses +system.cpu.dcache.overall_misses::total 9968106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,307 +786,307 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks -system.cpu.dcache.writebacks::total 5470621 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks +system.cpu.dcache.writebacks::total 5470632 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits -system.cpu.icache.overall_hits::total 32274508 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses -system.cpu.icache.overall_misses::total 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits +system.cpu.icache.overall_hits::total 32274679 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses +system.cpu.icache.overall_misses::total 1150 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 448 # number of writebacks system.cpu.icache.writebacks::total 448 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4986166 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5293297 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 266998 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 140 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074663 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 148 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11219.998633 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5292017 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14707 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 359.829809 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.098130 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.680780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.684814 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 64 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14495 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits -system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses -system.cpu.l2cache.overall_misses::total 4306 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180526200 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 5457195 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5457195 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 11011 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 11011 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225669 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225669 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 205 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241856 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5241856 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 205 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5467525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5467730 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 205 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5467525 # number of overall hits +system.cpu.l2cache.overall_hits::total 5467730 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 501 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 501 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 702 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3118 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 3118 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3619 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4321 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3619 # number of overall misses +system.cpu.l2cache.overall_misses::total 4321 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 106500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 106500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63936500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 63936500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58121500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58121500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 619277500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 619277500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58121500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 683214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 741335500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58121500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 683214000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 741335500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226170 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226170 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244974 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244974 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.773980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.773980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,167 +1094,167 @@ system.cpu.l2cache.blocked::no_targets 0 # nu system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks -system.cpu.l2cache.writebacks::total 104 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks +system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 30 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 188 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 188 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 189 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316628 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316628 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3431 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3431 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 320760 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1087453464 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53854500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53854500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 636757000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 690611500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53854500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 636757000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1778064964 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318864 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318663 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18190 # Transaction distribution -system.membus.trans_dist::WritebackDirty 104 # Transaction distribution -system.membus.trans_dist::CleanEvict 36 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18200 # Transaction distribution +system.membus.trans_dist::WritebackDirty 106 # Transaction distribution +system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::ReadExReq 342 # Transaction distribution system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18537 # Request fanout histogram +system.membus.snoop_fanout::samples 18549 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18537 # Request fanout histogram -system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18549 # Request fanout histogram +system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 48f2e7ba9..716a9adc9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066079 # Number of seconds simulated -sim_ticks 66079350000 # Number of ticks simulated -final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065833 # Number of seconds simulated +sim_ticks 65832730500 # Number of ticks simulated +final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185548 # Simulator instruction rate (inst/s) -host_op_rate 326721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77606283 # Simulator tick rate (ticks/s) -host_mem_usage 417148 # Number of bytes of host memory used -host_seconds 851.47 # Real time elapsed on the host +host_inst_rate 190384 # Simulator instruction rate (inst/s) +host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79331786 # Simulator tick rate (ticks/s) +host_mem_usage 416808 # Number of bytes of host memory used +host_seconds 829.84 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19520 # Number of bytes written to this memory -system.physmem.bytes_written::total 19520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29575 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1054732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28644350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29699081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 295402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1054732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28644350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29994484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 305 # Number of write requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1940 # Per bank write bursts -system.physmem.perBankRdBursts::1 2080 # Per bank write bursts -system.physmem.perBankRdBursts::2 2040 # Per bank write bursts -system.physmem.perBankRdBursts::3 1947 # Per bank write bursts -system.physmem.perBankRdBursts::4 2062 # Per bank write bursts +system.physmem.perBankRdBursts::0 1947 # Per bank write bursts +system.physmem.perBankRdBursts::1 2076 # Per bank write bursts +system.physmem.perBankRdBursts::2 2053 # Per bank write bursts +system.physmem.perBankRdBursts::3 1954 # Per bank write bursts +system.physmem.perBankRdBursts::4 2067 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1870 # Per bank write bursts -system.physmem.perBankRdBursts::8 1951 # Per bank write bursts -system.physmem.perBankRdBursts::9 1941 # Per bank write bursts +system.physmem.perBankRdBursts::7 1868 # Per bank write bursts +system.physmem.perBankRdBursts::8 1952 # Per bank write bursts +system.physmem.perBankRdBursts::9 1938 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts system.physmem.perBankRdBursts::14 1826 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 26 # Per bank write bursts -system.physmem.perBankWrBursts::1 125 # Per bank write bursts -system.physmem.perBankWrBursts::2 27 # Per bank write bursts -system.physmem.perBankWrBursts::3 24 # Per bank write bursts +system.physmem.perBankWrBursts::0 25 # Per bank write bursts +system.physmem.perBankWrBursts::1 120 # Per bank write bursts +system.physmem.perBankWrBursts::2 28 # Per bank write bursts +system.physmem.perBankWrBursts::3 32 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 3 # Per bank write bursts -system.physmem.perBankWrBursts::6 18 # Per bank write bursts -system.physmem.perBankWrBursts::7 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 2 # Per bank write bursts +system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66079146500 # Total gap between requests +system.physmem.totGap 65832525500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,12 +97,12 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,12 +147,12 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,355 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 685.122783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 477.283945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 398.354531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 431 14.99% 14.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 281 9.77% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 140 4.87% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 134 4.66% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 130 4.52% 38.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 125 4.35% 43.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.68% 45.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 84 2.92% 48.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1473 51.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1904.687500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.337942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.888425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.900644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.181454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3 18.75% 18.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 10 62.50% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 407578000 # Total ticks spent queuing -system.physmem.totMemAccLat 979678000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13357.96 # Average queueing delay per DRAM burst +system.physmem.totQLat 411710000 # Total ticks spent queuing +system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32107.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.50 # Average write queue length when enqueuing -system.physmem.readRowHits 27718 # Number of row buffer hits during reads -system.physmem.writeRowHits 199 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.25 # Row buffer hit rate for writes -system.physmem.avgGap 2133719.09 # Average gap between requests -system.physmem.pageHitRate 90.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11095560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5886045 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 112990500 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing +system.physmem.readRowHits 27751 # Number of row buffer hits during reads +system.physmem.writeRowHits 206 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes +system.physmem.avgGap 2125481.08 # Average gap between requests +system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 311007840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 261882510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17017920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 979925760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 266852640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15064489440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 17032599375 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.759790 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65460562250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23034750 # Time in different power states -system.physmem_0.memoryStateTime::REF 131986000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62616842500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 694916500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 463599750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2148970500 # Time in different power states -system.physmem_1.actEnergy 9481920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5024580 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104865180 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.950589 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states +system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states +system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 381691440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 255809160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 19980960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1151008410 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 399268320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14907041175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17234823375 # Total energy per rank (pJ) -system.physmem_1.averagePower 260.820111 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65463256000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 30077000 # Time in different power states -system.physmem_1.memoryStateTime::REF 162078000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61901089500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1039749000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 422083750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2524272750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40670761 # Number of BP lookups -system.cpu.branchPred.condPredicted 40670761 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1447235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26704882 # Number of BTB lookups +system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) +system.physmem_1.averagePower 261.179341 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states +system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40426123 # Number of BP lookups +system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6058055 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92918 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26704882 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21174798 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5530084 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 547932 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 132158701 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131665462 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30720551 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 221310466 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40670761 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27232853 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99729501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3011659 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 476 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6367 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 115460 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 59 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29905952 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.409240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66113924 50.06% 50.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4057337 3.07% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3620378 2.74% 55.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6125698 4.64% 60.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7769884 5.88% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5562288 4.21% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3378570 2.56% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2898316 2.19% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32552071 24.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307742 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.674581 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15424627 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64723504 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40539404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9885102 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1505829 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 364367574 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1505829 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20975204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11377644 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44575622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53625771 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 354569179 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16511 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 791289 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46695905 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5223216 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 357047318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939748965 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 578695140 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22535 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77834571 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 494 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 495 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64563941 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112883257 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38651230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51754424 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9024100 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 345545955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 318634973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172634 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 67357749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 104786759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3813 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 132078466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.412467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.166876 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 36007190 27.26% 27.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20156467 15.26% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17165000 13.00% 55.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17631185 13.35% 68.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15357300 11.63% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12905365 9.77% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6726655 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4095436 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2033868 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 132078466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366214 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3544032 86.41% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 189377 4.62% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 6 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1660 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182328648 57.22% 57.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11540 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 353 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101489286 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34764932 10.91% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 469 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6130 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued -system.cpu.iq.rate 2.411003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4101289 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012871 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773603045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 19290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 322694382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8540 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued +system.cpu.iq.rate 2.414517 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67270 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 64283 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7211478 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3969 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140998 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1505829 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8247421 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3042364 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 345550213 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112883257 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38651230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1745 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2963 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3048582 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 64283 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 545574 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1082259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1627833 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316133024 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100718075 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2501949 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135067596 # number of memory reference insts executed -system.cpu.iew.exec_branches 32155475 # Number of branches executed -system.cpu.iew.exec_stores 34349521 # Number of stores executed -system.cpu.iew.exec_rate 2.392071 # Inst execution rate -system.cpu.iew.wb_sent 314966910 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314309567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238188610 # num instructions producing a value -system.cpu.iew.wb_consumers 344086280 # num instructions consuming a value -system.cpu.iew.wb_rate 2.378274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692235 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 67483313 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed +system.cpu.iew.exec_branches 32108537 # Number of branches executed +system.cpu.iew.exec_stores 34312066 # Number of stores executed +system.cpu.iew.exec_rate 2.396197 # Inst execution rate +system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237724315 # num instructions producing a value +system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value +system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1453904 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122408865 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.272650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.045643 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57244612 46.77% 46.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16526306 13.50% 60.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11253907 9.19% 69.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8747083 7.15% 76.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2074138 1.69% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764583 1.44% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 930878 0.76% 80.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726504 0.59% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23140854 18.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122408865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,451 +592,451 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23140854 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 444943788 # The number of ROB reads -system.cpu.rob.rob_writes 701094607 # The number of ROB writes -system.cpu.timesIdled 892 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 443221536 # The number of ROB reads +system.cpu.rob.rob_writes 698006714 # The number of ROB writes +system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.836508 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.836508 # CPI: Total CPI of All Threads -system.cpu.ipc 1.195446 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.195446 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 503639899 # number of integer regfile reads -system.cpu.int_regfile_writes 248370602 # number of integer regfile writes -system.cpu.fp_regfile_reads 4288 # number of floating regfile reads -system.cpu.fp_regfile_writes 677 # number of floating regfile writes -system.cpu.cc_regfile_reads 109192725 # number of cc regfile reads -system.cpu.cc_regfile_writes 65564647 # number of cc regfile writes -system.cpu.misc_regfile_reads 202344104 # number of misc regfile reads +system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads +system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502917784 # number of integer regfile reads +system.cpu.int_regfile_writes 247848787 # number of integer regfile writes +system.cpu.fp_regfile_reads 4075 # number of floating regfile reads +system.cpu.fp_regfile_writes 819 # number of floating regfile writes +system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads +system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes +system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073334 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.317880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71743454 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077430 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.534715 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21320595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.317880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992998 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992998 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073306 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3441 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151138894 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151138894 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40397499 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40397499 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345955 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71743454 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71743454 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71743454 # number of overall hits -system.cpu.dcache.overall_hits::total 71743454 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693481 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693481 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787278 # number of overall misses -system.cpu.dcache.overall_misses::total 2787278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35599500993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35599500993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43090980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits +system.cpu.dcache.overall_hits::total 71520008 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses +system.cpu.dcache.overall_misses::total 2786939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74530732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74530732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74530732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74530732 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219409 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43429 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.052131 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066585 # number of writebacks -system.cpu.dcache.writebacks::total 2066585 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697929 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11919 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709848 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709848 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81878 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81878 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077430 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077430 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 871.416193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29904477 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26772.136974 # Average number of references to valid blocks. +system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks +system.cpu.dcache.writebacks::total 2066926 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81814 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077402 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077402 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077402 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077402 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24271228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24271228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3023849487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3023849487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27295077987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27295077987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 871.416193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1023 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 905 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.499512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59813021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59813021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29904477 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29904477 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29904477 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29904477 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29904477 # number of overall hits -system.cpu.icache.overall_hits::total 29904477 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses -system.cpu.icache.overall_misses::total 1475 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154630499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154630499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154630499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154630499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29905952 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29905952 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29905952 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29905952 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 104834.236610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 104834.236610 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 104834.236610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 104834.236610 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3285 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 910 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59528269 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59528269 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29762089 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29762089 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29762089 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29762089 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29762089 # number of overall hits +system.cpu.icache.overall_hits::total 29762089 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1485 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1485 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1485 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1485 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1485 # number of overall misses +system.cpu.icache.overall_misses::total 1485 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 149774999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 149774999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 149774999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 149774999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 149774999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 149774999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29763574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29763574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29763574 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29763574 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29763574 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29763574 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100858.585185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100858.585185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100858.585185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100858.585185 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2965 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 219 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 211.785714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 94 # number of writebacks -system.cpu.icache.writebacks::total 94 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 358 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 358 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 358 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 358 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 358 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1117 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1117 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1117 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1117 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1117 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1117 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115157499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 115157499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115157499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 115157499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115157499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 115157499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 103095.343778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 103095.343778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 364 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 364 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 364 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 364 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 114880499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 114880499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 114880499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 114880499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 114880499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 114880499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102480.373773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102480.373773 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 694 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21600.967235 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 21678.088627 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4121221 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30681 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.326619 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 134.324859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.261837 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.389241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20887.316157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.637430 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.659209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2.638364 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 712.370564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20963.079700 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021740 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.639742 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.661563 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29987 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29627 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29624 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915131 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33246329 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33246329 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066585 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066585 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 94 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 94 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52930 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52930 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 33245897 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33245897 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066926 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066926 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52858 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52858 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1994925 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1994925 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1994973 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1994973 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047855 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047883 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047831 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047859 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047855 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047883 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28997 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28997 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1089 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1089 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 578 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 578 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1089 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29575 # number of demand (read+write) misses +system.cpu.l2cache.overall_hits::cpu.data 2047831 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047859 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28990 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28990 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 581 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 581 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 30664 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1089 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29575 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses system.cpu.l2cache.overall_misses::total 30664 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2345855500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2345855500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113174000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 113174000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 87677000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 87677000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 113174000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2433532500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2546706500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 113174000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2433532500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2546706500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066585 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066585 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 94 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 94 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81927 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81927 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1117 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1117 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1995503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1117 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078547 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1117 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078547 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353937 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353937 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974933 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974933 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974933 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014236 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2345791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2345791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 112890000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 112890000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 92689500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 92689500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 112890000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2438480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2551370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 112890000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2438480500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2551370500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066926 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066926 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1121 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1121 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995554 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995554 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077402 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078523 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077402 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078523 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.354193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.354193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.975022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.975022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.975022 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014235 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974933 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014236 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.975022 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014235 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80899.937925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80899.937925 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103924.701561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103924.701561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 151690.311419 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 151690.311419 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83051.999087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83051.999087 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80917.247327 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80917.247327 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103284.537969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103284.537969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 159534.423408 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 159534.423408 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83204.099270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83204.099270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 305 # number of writebacks -system.cpu.l2cache.writebacks::total 305 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28997 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28997 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1089 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1089 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 578 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 578 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks +system.cpu.l2cache.writebacks::total 309 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28990 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28990 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1093 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1093 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 581 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 581 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055885500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055885500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 102284000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 102284000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 81897000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 81897000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102284000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2137782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2240066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102284000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2137782500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2240066500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 101960000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 101960000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 86879500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 86879500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2142770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2244730500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2142770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2244730500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151975 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073430 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2066890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 94 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 7138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265216960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265294464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079241 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000169 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013010 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078889 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 352 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079241 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142666500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116145000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31027 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 363 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1667 # Transaction distribution -system.membus.trans_dist::WritebackDirty 305 # Transaction distribution -system.membus.trans_dist::CleanEvict 58 # Transaction distribution -system.membus.trans_dist::ReadExReq 28997 # Transaction distribution -system.membus.trans_dist::ReadExResp 28997 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1667 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1674 # Transaction distribution +system.membus.trans_dist::WritebackDirty 309 # Transaction distribution +system.membus.trans_dist::CleanEvict 50 # Transaction distribution +system.membus.trans_dist::ReadExReq 28990 # Transaction distribution +system.membus.trans_dist::ReadExResp 28990 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 30664 # Request fanout histogram @@ -1049,9 +1049,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43847500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161573250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3b6bf0c6f..5f5ab2bca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600034500 # Number of ticks simulated -final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 368600047500 # Number of ticks simulated +final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 368828 # Simulator instruction rate (inst/s) -host_op_rate 399489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 268368313 # Simulator tick rate (ticks/s) -host_mem_usage 276836 # Number of bytes of host memory used -host_seconds 1373.49 # Real time elapsed on the host +host_inst_rate 377886 # Simulator instruction rate (inst/s) +host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274959159 # Simulator tick rate (ticks/s) +host_mem_usage 276756 # Number of bytes of host memory used +host_seconds 1340.56 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 144269 # Nu system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144269 # Number of read requests accepted system.physmem.writeReqs 97528 # Number of write requests accepted system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 6013 # Pe system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600009000 # Total gap between requests +system.physmem.totGap 368600022000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -228,12 +228,12 @@ system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577413000 # Total ticks spent queuing -system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3577410500 # Total ticks spent queuing +system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s @@ -248,47 +248,47 @@ system.physmem.readRowHits 110541 # Nu system.physmem.writeRowHits 67141 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.28 # Average gap between requests +system.physmem.avgGap 1524419.34 # Average gap between requests system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209476 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.209478 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172732 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.172742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 132103819 # Number of BP lookups system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect @@ -303,7 +303,7 @@ system.cpu.branchPred.indirectHits 3883028 # Nu system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,8 +424,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200069 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737200095 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed @@ -473,16 +473,16 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -491,11 +491,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -504,10 +504,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits -system.cpu.dcache.overall_hits::total 168106742 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits +system.cpu.dcache.overall_hits::total 168106741 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses @@ -518,16 +518,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512467 # n system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -536,10 +536,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -550,14 +550,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,16 +584,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -604,24 +604,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id @@ -631,45 +631,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits -system.cpu.icache.overall_hits::total 199149017 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits +system.cpu.icache.overall_hits::total 199149019 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,34 +684,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20050 system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy @@ -724,7 +724,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_misses::total 144283 # nu system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses system.cpu.l2cache.overall_misses::total 144283 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) @@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123797 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -835,17 +835,17 @@ system.cpu.l2cache.demand_mshr_misses::total 144269 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses @@ -859,17 +859,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -877,7 +877,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution @@ -917,7 +917,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 43291 # Transaction distribution system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution system.membus.trans_dist::CleanEvict 12615 # Transaction distribution @@ -940,9 +940,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 36fb98963..3dfc36814 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236034 # Number of seconds simulated -sim_ticks 236034256000 # Number of ticks simulated -final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.236024 # Number of seconds simulated +sim_ticks 236023688000 # Number of ticks simulated +final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253188 # Simulator instruction rate (inst/s) -host_op_rate 274292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118283576 # Simulator tick rate (ticks/s) -host_mem_usage 302048 # Number of bytes of host memory used -host_seconds 1995.49 # Real time elapsed on the host +host_inst_rate 256452 # Simulator instruction rate (inst/s) +host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119803336 # Simulator tick rate (ticks/s) +host_mem_usage 301968 # Number of bytes of host memory used +host_seconds 1970.09 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory -system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory -system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430064 # Number of read requests accepted -system.physmem.writeReqs 291274 # Number of write requests accepted -system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue -system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory +system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory +system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430392 # Number of read requests accepted +system.physmem.writeReqs 291097 # Number of write requests accepted +system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27217 # Per bank write bursts -system.physmem.perBankRdBursts::1 26580 # Per bank write bursts -system.physmem.perBankRdBursts::2 25459 # Per bank write bursts -system.physmem.perBankRdBursts::3 32933 # Per bank write bursts -system.physmem.perBankRdBursts::4 28005 # Per bank write bursts -system.physmem.perBankRdBursts::5 30095 # Per bank write bursts -system.physmem.perBankRdBursts::6 25324 # Per bank write bursts -system.physmem.perBankRdBursts::7 24336 # Per bank write bursts -system.physmem.perBankRdBursts::8 25637 # Per bank write bursts -system.physmem.perBankRdBursts::9 25661 # Per bank write bursts -system.physmem.perBankRdBursts::10 25768 # Per bank write bursts -system.physmem.perBankRdBursts::11 26242 # Per bank write bursts -system.physmem.perBankRdBursts::12 27581 # Per bank write bursts -system.physmem.perBankRdBursts::13 26014 # Per bank write bursts -system.physmem.perBankRdBursts::14 24864 # Per bank write bursts -system.physmem.perBankRdBursts::15 25798 # Per bank write bursts -system.physmem.perBankWrBursts::0 18651 # Per bank write bursts -system.physmem.perBankWrBursts::1 18268 # Per bank write bursts -system.physmem.perBankWrBursts::2 17926 # Per bank write bursts -system.physmem.perBankWrBursts::3 17983 # Per bank write bursts -system.physmem.perBankWrBursts::4 18558 # Per bank write bursts -system.physmem.perBankWrBursts::5 18375 # Per bank write bursts -system.physmem.perBankWrBursts::6 17786 # Per bank write bursts -system.physmem.perBankWrBursts::7 17681 # Per bank write bursts -system.physmem.perBankWrBursts::8 18027 # Per bank write bursts -system.physmem.perBankWrBursts::9 17737 # Per bank write bursts -system.physmem.perBankWrBursts::10 18114 # Per bank write bursts -system.physmem.perBankWrBursts::11 18781 # Per bank write bursts -system.physmem.perBankWrBursts::12 18716 # Per bank write bursts -system.physmem.perBankWrBursts::13 18163 # Per bank write bursts -system.physmem.perBankWrBursts::14 18303 # Per bank write bursts -system.physmem.perBankWrBursts::15 18163 # Per bank write bursts +system.physmem.perBankRdBursts::0 27300 # Per bank write bursts +system.physmem.perBankRdBursts::1 26589 # Per bank write bursts +system.physmem.perBankRdBursts::2 25489 # Per bank write bursts +system.physmem.perBankRdBursts::3 32817 # Per bank write bursts +system.physmem.perBankRdBursts::4 28238 # Per bank write bursts +system.physmem.perBankRdBursts::5 30052 # Per bank write bursts +system.physmem.perBankRdBursts::6 25322 # Per bank write bursts +system.physmem.perBankRdBursts::7 24428 # Per bank write bursts +system.physmem.perBankRdBursts::8 25638 # Per bank write bursts +system.physmem.perBankRdBursts::9 25508 # Per bank write bursts +system.physmem.perBankRdBursts::10 25695 # Per bank write bursts +system.physmem.perBankRdBursts::11 26146 # Per bank write bursts +system.physmem.perBankRdBursts::12 27543 # Per bank write bursts +system.physmem.perBankRdBursts::13 26122 # Per bank write bursts +system.physmem.perBankRdBursts::14 24924 # Per bank write bursts +system.physmem.perBankRdBursts::15 25996 # Per bank write bursts +system.physmem.perBankWrBursts::0 18688 # Per bank write bursts +system.physmem.perBankWrBursts::1 18252 # Per bank write bursts +system.physmem.perBankWrBursts::2 17892 # Per bank write bursts +system.physmem.perBankWrBursts::3 17877 # Per bank write bursts +system.physmem.perBankWrBursts::4 18635 # Per bank write bursts +system.physmem.perBankWrBursts::5 18189 # Per bank write bursts +system.physmem.perBankWrBursts::6 17877 # Per bank write bursts +system.physmem.perBankWrBursts::7 17743 # Per bank write bursts +system.physmem.perBankWrBursts::8 17943 # Per bank write bursts +system.physmem.perBankWrBursts::9 17697 # Per bank write bursts +system.physmem.perBankWrBursts::10 18014 # Per bank write bursts +system.physmem.perBankWrBursts::11 18785 # Per bank write bursts +system.physmem.perBankWrBursts::12 18684 # Per bank write bursts +system.physmem.perBankWrBursts::13 18184 # Per bank write bursts +system.physmem.perBankWrBursts::14 18324 # Per bank write bursts +system.physmem.perBankWrBursts::15 18279 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236034203500 # Total gap between requests +system.physmem.totGap 236023635500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430064 # Read request sizes (log2) +system.physmem.readPktSize::6 430392 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291274 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291097 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,124 +198,127 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads -system.physmem.totQLat 14213030846 # Total ticks spent queuing -system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads +system.physmem.totQLat 14230918095 # Total ticks spent queuing +system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing -system.physmem.readRowHits 307655 # Number of row buffer hits during reads -system.physmem.writeRowHits 82023 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes -system.physmem.avgGap 327217.20 # Average gap between requests -system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.569128 # Core power per rank (mW) -system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states -system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states -system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ) -system.physmem_1.averagePower 468.321620 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states -system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174591760 # Number of BP lookups -system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 308090 # Number of row buffer hits during reads +system.physmem.writeRowHits 82180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes +system.physmem.avgGap 327134.07 # Average gap between requests +system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.494648 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states +system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states +system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) +system.physmem_1.averagePower 467.936931 # Core power per rank (mW) +system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states +system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594111 # Number of BP lookups +system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -345,7 +348,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -375,7 +378,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -405,7 +408,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -436,241 +439,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472068513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 472047377 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued -system.cpu.iq.rate 1.289866 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued +system.cpu.iq.rate 1.289985 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492787 # number of nop insts executed -system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed -system.cpu.iew.exec_branches 131261458 # Number of branches executed -system.cpu.iew.exec_stores 60913564 # Number of stores executed -system.cpu.iew.exec_rate 1.267626 # Inst execution rate -system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349559163 # num instructions producing a value -system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492981 # number of nop insts executed +system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed +system.cpu.iew.exec_branches 131264327 # Number of branches executed +system.cpu.iew.exec_stores 60922697 # Number of stores executed +system.cpu.iew.exec_rate 1.267746 # Inst execution rate +system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349573647 # num instructions producing a value +system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value +system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -720,559 +723,560 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096128717 # The number of ROB reads -system.cpu.rob.rob_writes 1328290478 # The number of ROB writes -system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1096141105 # The number of ROB reads +system.cpu.rob.rob_writes 1328357052 # The number of ROB writes +system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610109745 # number of integer regfile reads -system.cpu.int_regfile_writes 327329948 # number of integer regfile writes +system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610147261 # number of integer regfile reads +system.cpu.int_regfile_writes 327343686 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads -system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes -system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads +system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes +system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817163 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits -system.cpu.dcache.overall_hits::total 165885650 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits +system.cpu.dcache.overall_hits::total 165891987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses -system.cpu.dcache.overall_misses::total 7356185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses +system.cpu.dcache.overall_misses::total 7356950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks -system.cpu.dcache.writebacks::total 2817297 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits +system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks +system.cpu.dcache.writebacks::total 2817163 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817826 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563184494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37563184494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003569 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016266 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9206.825332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76619 # number of replacements -system.cpu.icache.tags.tagsinuse 466.071602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235190778 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77131 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3049.238024 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116612189500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.071602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910296 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910296 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76621 # number of replacements +system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470630395 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470630395 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235190778 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235190778 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235190778 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235190778 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235190778 # number of overall hits -system.cpu.icache.overall_hits::total 235190778 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 85841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 85841 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 85841 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 85841 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 85841 # number of overall misses -system.cpu.icache.overall_misses::total 85841 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1941915678 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1941915678 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1941915678 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1941915678 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1941915678 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1941915678 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235276619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235276619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235276619 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235276619 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235276619 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235276619 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76619 # number of writebacks -system.cpu.icache.writebacks::total 76619 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8683 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8683 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8683 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8683 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8683 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77158 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77158 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77158 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77158 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77158 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77158 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1536678279 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1536678279 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1536678279 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1536678279 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1536678279 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1536678279 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits +system.cpu.icache.overall_hits::total 235191085 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 86061 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 86061 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 86061 # number of overall misses +system.cpu.icache.overall_misses::total 86061 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1945774184 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1945774184 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1945774184 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1945774184 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1945774184 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1945774184 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235277146 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235277146 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235277146 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22609.244420 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22609.244420 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22609.244420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22609.244420 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 200857 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1531 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7099 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76621 # number of writebacks +system.cpu.icache.writebacks::total 76621 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19915.994181 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19915.994181 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8510000 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8511429 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 428 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743291 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 389594 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15007.037789 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2698812 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405195 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.660526 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 389920 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14932.547255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.490534 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911410 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 98 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 672 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5433 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6587 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2565 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.005981 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946228 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95366335 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95366335 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2351800 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2351800 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 518252 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 518252 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516857 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516857 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 67161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130903 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2130903 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 67161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2647760 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2714921 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 67161 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2647760 # number of overall hits -system.cpu.l2cache.overall_hits::total 2714921 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5168 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5168 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9964 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 9964 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164881 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 164881 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9964 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170049 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180013 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9964 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170049 # number of overall misses -system.cpu.l2cache.overall_misses::total 180013 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 20500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 20500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 668599000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 668599000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1018287500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1018287500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371092500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371092500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1018287500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16039691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17057979000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1018287500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16039691500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17057979000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2351800 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2351800 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 518252 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 518252 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 522025 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 522025 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77125 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 77125 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295784 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2295784 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 77125 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2817809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2894934 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 77125 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2817809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2894934 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2356317 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 513605 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 513605 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516771 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516771 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67113 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 67113 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130678 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2130678 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 67113 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2647449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2714562 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 67113 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2647449 # number of overall hits +system.cpu.l2cache.overall_hits::total 2714562 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 5213 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5213 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10017 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10017 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 165013 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 165013 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10017 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 170226 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180243 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10017 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 170226 # number of overall misses +system.cpu.l2cache.overall_misses::total 180243 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 669742000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 669742000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1015207000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1015207000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371129000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371129000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1015207000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16040871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17056078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1015207000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16040871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17056078000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356317 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2356317 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 513605 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 513605 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 521984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 521984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77130 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 77130 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295691 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2295691 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 77130 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2817675 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2894805 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 77130 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2817675 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2894805 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009900 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009900 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129193 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129193 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071819 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071819 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129193 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.060348 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062182 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129193 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.060348 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062182 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 759.259259 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 759.259259 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129372.871517 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129372.871517 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102196.657969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102196.657969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93225.371632 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93225.371632 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94759.706243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94759.706243 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009987 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009987 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129872 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129872 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071879 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071879 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129872 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.060414 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062264 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129872 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.060414 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062264 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 741.379310 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 741.379310 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128475.350086 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128475.350086 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101348.407707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101348.407707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93151.018405 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93151.018405 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94628.240764 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94628.240764 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 2063 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 291274 # number of writebacks -system.cpu.l2cache.writebacks::total 291274 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1581 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1581 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4441 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4441 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6022 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6022 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355324 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 355324 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3587 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3587 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9956 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9956 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160440 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160440 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 164027 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 173983 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 164027 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355324 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 529307 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21295211595 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 417500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 417500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 461178500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 461178500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 956729500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 956729500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14002333000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14002333000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 956729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14463511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15420241000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 956729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14463511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 36715452595 # number of overall MSHR miss cycles +system.cpu.l2cache.unused_prefetches 2009 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 291097 # number of writebacks +system.cpu.l2cache.writebacks::total 291097 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1528 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1528 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4483 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4483 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6011 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6015 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6011 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6015 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355832 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 355832 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160530 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160530 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164215 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530060 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21330424894 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 451500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 451500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 469308000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 469308000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 954360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 954360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13996060500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13996060500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 954360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14465368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15419729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 954360500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14465368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36750153894 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 791889 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 792623 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426481 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution -system.membus.trans_dist::CleanEvict 98320 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426709 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution +system.membus.trans_dist::CleanEvict 98823 # Transaction distribution system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3582 # Transaction distribution -system.membus.trans_dist::ReadExResp 3582 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3682 # Transaction distribution +system.membus.trans_dist::ReadExResp 3682 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430096 # Request fanout histogram +system.membus.snoop_fanout::samples 430424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430096 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430424 # Request fanout histogram +system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 32b980d52..1d6cdc3c5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487015 # Number of seconds simulated -sim_ticks 487015166000 # Number of ticks simulated -final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487172 # Number of seconds simulated +sim_ticks 487172057000 # Number of ticks simulated +final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149671 # Simulator instruction rate (inst/s) -host_op_rate 276966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88156571 # Simulator tick rate (ticks/s) -host_mem_usage 323840 # Number of bytes of host memory used -host_seconds 5524.43 # Real time elapsed on the host +host_inst_rate 151495 # Simulator instruction rate (inst/s) +host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89259825 # Simulator tick rate (ticks/s) +host_mem_usage 322228 # Number of bytes of host memory used +host_seconds 5457.91 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory -system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory -system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387502 # Number of read requests accepted -system.physmem.writeReqs 295435 # Number of write requests accepted -system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue -system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory +system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387585 # Number of read requests accepted +system.physmem.writeReqs 295461 # Number of write requests accepted +system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue +system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24677 # Per bank write bursts -system.physmem.perBankRdBursts::1 26454 # Per bank write bursts -system.physmem.perBankRdBursts::2 24704 # Per bank write bursts -system.physmem.perBankRdBursts::3 24551 # Per bank write bursts -system.physmem.perBankRdBursts::4 23256 # Per bank write bursts -system.physmem.perBankRdBursts::5 23627 # Per bank write bursts -system.physmem.perBankRdBursts::6 24680 # Per bank write bursts -system.physmem.perBankRdBursts::7 24455 # Per bank write bursts -system.physmem.perBankRdBursts::8 23806 # Per bank write bursts -system.physmem.perBankRdBursts::9 23529 # Per bank write bursts -system.physmem.perBankRdBursts::10 24814 # Per bank write bursts -system.physmem.perBankRdBursts::11 23994 # Per bank write bursts -system.physmem.perBankRdBursts::12 23307 # Per bank write bursts -system.physmem.perBankRdBursts::13 23001 # Per bank write bursts -system.physmem.perBankRdBursts::14 24016 # Per bank write bursts -system.physmem.perBankRdBursts::15 24323 # Per bank write bursts -system.physmem.perBankWrBursts::0 19004 # Per bank write bursts -system.physmem.perBankWrBursts::1 19961 # Per bank write bursts -system.physmem.perBankWrBursts::2 19032 # Per bank write bursts -system.physmem.perBankWrBursts::3 19001 # Per bank write bursts -system.physmem.perBankWrBursts::4 18129 # Per bank write bursts -system.physmem.perBankWrBursts::5 18443 # Per bank write bursts -system.physmem.perBankWrBursts::6 19167 # Per bank write bursts -system.physmem.perBankWrBursts::7 19127 # Per bank write bursts -system.physmem.perBankWrBursts::8 18708 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18897 # Per bank write bursts -system.physmem.perBankWrBursts::11 17782 # Per bank write bursts -system.physmem.perBankWrBursts::12 17420 # Per bank write bursts -system.physmem.perBankWrBursts::13 16998 # Per bank write bursts -system.physmem.perBankWrBursts::14 17822 # Per bank write bursts -system.physmem.perBankWrBursts::15 17973 # Per bank write bursts +system.physmem.perBankRdBursts::0 24645 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24674 # Per bank write bursts +system.physmem.perBankRdBursts::3 24501 # Per bank write bursts +system.physmem.perBankRdBursts::4 23296 # Per bank write bursts +system.physmem.perBankRdBursts::5 23619 # Per bank write bursts +system.physmem.perBankRdBursts::6 24746 # Per bank write bursts +system.physmem.perBankRdBursts::7 24503 # Per bank write bursts +system.physmem.perBankRdBursts::8 23866 # Per bank write bursts +system.physmem.perBankRdBursts::9 23595 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 23982 # Per bank write bursts +system.physmem.perBankRdBursts::12 23298 # Per bank write bursts +system.physmem.perBankRdBursts::13 23005 # Per bank write bursts +system.physmem.perBankRdBursts::14 24008 # Per bank write bursts +system.physmem.perBankRdBursts::15 24312 # Per bank write bursts +system.physmem.perBankWrBursts::0 19007 # Per bank write bursts +system.physmem.perBankWrBursts::1 19956 # Per bank write bursts +system.physmem.perBankWrBursts::2 19034 # Per bank write bursts +system.physmem.perBankWrBursts::3 18984 # Per bank write bursts +system.physmem.perBankWrBursts::4 18157 # Per bank write bursts +system.physmem.perBankWrBursts::5 18431 # Per bank write bursts +system.physmem.perBankWrBursts::6 19162 # Per bank write bursts +system.physmem.perBankWrBursts::7 19114 # Per bank write bursts +system.physmem.perBankWrBursts::8 18737 # Per bank write bursts +system.physmem.perBankWrBursts::9 17973 # Per bank write bursts +system.physmem.perBankWrBursts::10 18902 # Per bank write bursts +system.physmem.perBankWrBursts::11 17777 # Per bank write bursts +system.physmem.perBankWrBursts::12 17406 # Per bank write bursts +system.physmem.perBankWrBursts::13 16997 # Per bank write bursts +system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487015078500 # Total gap between requests +system.physmem.totGap 487171969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387502 # Read request sizes (log2) +system.physmem.readPktSize::6 387585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295461 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -194,217 +194,214 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads -system.physmem.totQLat 9773520500 # Total ticks spent queuing -system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads +system.physmem.totQLat 9753002000 # Total ticks spent queuing +system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing -system.physmem.readRowHits 316194 # Number of row buffer hits during reads -system.physmem.writeRowHits 220049 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes -system.physmem.avgGap 713118.60 # Average gap between requests -system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.564568 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states -system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.116816 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 298029097 # Number of BP lookups -system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 316112 # Number of row buffer hits during reads +system.physmem.writeRowHits 219918 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 713234.50 # Average gap between requests +system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.552673 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states +system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.472734 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states +system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297986094 # Number of BP lookups +system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974030333 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974344115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available @@ -435,22 +432,22 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued @@ -473,84 +470,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued -system.cpu.iq.rate 2.052607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued +system.cpu.iq.rate 2.052034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed -system.cpu.iew.exec_branches 185215439 # Number of branches executed -system.cpu.iew.exec_stores 178800268 # Number of stores executed -system.cpu.iew.exec_rate 1.997714 # Inst execution rate -system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457208218 # num instructions producing a value -system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value -system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed +system.cpu.iew.exec_branches 185192217 # Number of branches executed +system.cpu.iew.exec_stores 178842517 # Number of stores executed +system.cpu.iew.exec_rate 1.997151 # Inst execution rate +system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457137045 # num instructions producing a value +system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,495 +597,495 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187574492 # The number of ROB reads -system.cpu.rob.rob_writes 4974168269 # The number of ROB writes -system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3187918398 # The number of ROB reads +system.cpu.rob.rob_writes 4974407602 # The number of ROB writes +system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads -system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes -system.cpu.fp_regfile_reads 239166 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads -system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads +system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads +system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes +system.cpu.fp_regfile_reads 236699 # number of floating regfile reads +system.cpu.fp_regfile_writes 4 # number of floating regfile writes +system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads +system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546002 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546054 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits -system.cpu.dcache.overall_hits::total 420917748 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses -system.cpu.dcache.overall_misses::total 3352814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits +system.cpu.dcache.overall_hits::total 421109343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses +system.cpu.dcache.overall_misses::total 3358592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks -system.cpu.dcache.writebacks::total 2338096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 800891 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 800891 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 800891 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766370 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766370 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785553 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785553 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551923 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551923 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551923 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37596158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks +system.cpu.dcache.writebacks::total 2337949 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551872 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551872 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3937 # number of replacements -system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21276.538911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21276.538911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32451.737319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32451.737319 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4004 # number of replacements +system.cpu.icache.tags.tagsinuse 1085.037164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216431030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5719 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37844.208778 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1085.037164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216368192 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216368192 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216368192 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216368192 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216368192 # number of overall hits -system.cpu.icache.overall_hits::total 216368192 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9822 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9822 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9822 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9822 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9822 # number of overall misses -system.cpu.icache.overall_misses::total 9822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 562018500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 562018500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 562018500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 562018500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216378014 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216378014 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216378014 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216378014 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1557 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432889551 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432889551 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216431266 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216431266 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216431266 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216431266 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216431266 # number of overall hits +system.cpu.icache.overall_hits::total 216431266 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9783 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9783 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9783 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9783 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9783 # number of overall misses +system.cpu.icache.overall_misses::total 9783 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 586259000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 586259000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 586259000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 586259000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 586259000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 586259000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216441049 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216441049 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216441049 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216441049 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57220.372633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57220.372633 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3937 # number of writebacks -system.cpu.icache.writebacks::total 3937 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2342 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2342 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2342 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2342 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2342 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2342 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7480 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7480 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7480 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7480 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7480 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7480 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 378895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 378895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378895000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 378895000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000035 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50654.411765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50654.411765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 355911 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30630.560827 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4712762 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388679 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.125075 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 82947046000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 71.927824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.909939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30366.723064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002195 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005857 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.926719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.934771 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59926.300726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59926.300726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59926.300726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59926.300726 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 654 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 486 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 486 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 4004 # number of writebacks +system.cpu.icache.writebacks::total 4004 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2330 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2330 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2330 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2330 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2330 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2330 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7453 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7453 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7453 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7453 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7453 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7453 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386965000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 386965000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386965000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 386965000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386965000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 386965000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51920.703073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51920.703073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 356023 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30628.268694 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4712326 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388791 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.120461 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 83034365000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 73.003370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 193.382004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30361.883320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002228 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.926571 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31129 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41200319 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41200319 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2338096 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2338096 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3847 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3847 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1820 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1820 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577163 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577163 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3171 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3171 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587839 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587839 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3171 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2165002 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2168173 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3171 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2165002 # number of overall hits -system.cpu.l2cache.overall_hits::total 2168173 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206795 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206795 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2409 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2409 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178301 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 178301 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2409 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 385096 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387505 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2409 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 385096 # number of overall misses -system.cpu.l2cache.overall_misses::total 387505 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18229359500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18229359500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 331268000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 331268000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18228771500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18228771500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 331268000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 36458131000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36789399000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 331268000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 36458131000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36789399000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2338096 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2338096 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3847 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3847 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 783958 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 783958 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5580 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5580 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766140 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1766140 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2550098 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555678 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2550098 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555678 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002740 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002740 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263783 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263783 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.431720 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.431720 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100955 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100955 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.431720 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151012 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151625 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.431720 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151012 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151625 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6100 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88151.838778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88151.838778 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 137512.660855 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 137512.660855 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102235.946517 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102235.946517 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94939.159495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94939.159495 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 41197863 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41197863 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2337949 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2337949 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3908 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3908 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1714 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1714 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 577340 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 577340 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587646 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1587646 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2164986 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2168197 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2164986 # number of overall hits +system.cpu.l2cache.overall_hits::total 2168197 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206765 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206765 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2422 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2422 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178399 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 178399 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2422 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 385164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 387586 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2422 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 385164 # number of overall misses +system.cpu.l2cache.overall_misses::total 387586 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 61000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 61000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18232552000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18232552000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 339097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 339097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18206411000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18206411000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 339097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 36438963000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36778060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 339097000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 36438963000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36778060000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337949 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2337949 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1722 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1722 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 784105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 784105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5633 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5633 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766045 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1766045 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5633 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2550150 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2555783 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5633 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2550150 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2555783 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.004646 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.004646 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263696 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.263696 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429966 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429966 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101016 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101016 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429966 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151036 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151651 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429966 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151036 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151651 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7625 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7625 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88180.069161 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88180.069161 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 140007.018993 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 140007.018993 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102054.445372 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102054.445372 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94890.063109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94890.063109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295435 # number of writebacks -system.cpu.l2cache.writebacks::total 295435 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206795 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206795 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2409 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2409 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178301 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178301 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2409 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385096 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387505 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2409 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385096 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387505 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16161409500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16161409500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307178000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307178000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16445761500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16445761500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307178000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32607171000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32914349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307178000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32607171000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32914349000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295461 # number of writebacks +system.cpu.l2cache.writebacks::total 295461 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2422 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2422 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178399 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178399 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387586 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 159000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 159000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16164902000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16164902000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 314877000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 314877000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16422421000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16422421000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 314877000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32587323000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32902200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 314877000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32587323000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32902200000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151625 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357811 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429966 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101016 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101016 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151651 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19875 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19875 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 616768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312838336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313455104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357843 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19025984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915348 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009238 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.095698 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution -system.membus.trans_dist::CleanEvict 57541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 206792 # Transaction distribution -system.membus.trans_dist::ReadExResp 206792 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180821 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution +system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 206764 # Transaction distribution +system.membus.trans_dist::ReadExResp 206764 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387510 # Request fanout histogram +system.membus.snoop_fanout::samples 387594 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387510 # Request fanout histogram -system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387594 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index d7f32d52d..b2bc0dd63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284094 # Simulator instruction rate (inst/s) -host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 234325505 # Simulator tick rate (ticks/s) -host_mem_usage 279956 # Number of bytes of host memory used -host_seconds 961.08 # Real time elapsed on the host +host_inst_rate 289736 # Simulator instruction rate (inst/s) +host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238979319 # Simulator tick rate (ticks/s) +host_mem_usage 279872 # Number of bytes of host memory used +host_seconds 942.37 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # By system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 232482000 # Total ticks spent queuing -system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 232471000 # Total ticks spent queuing +system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -228,28 +228,28 @@ system.physmem_0.preEnergy 2504700 # En system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071438 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071435 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -590,12 +590,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -620,12 +620,12 @@ system.cpu.icache.demand_misses::cpu.inst 40126 # n system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses @@ -638,12 +638,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,33 +658,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy @@ -728,16 +728,16 @@ system.cpu.l2cache.overall_misses::cpu.data 4204 # system.cpu.l2cache.overall_misses::total 7630 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -768,16 +768,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,16 +808,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -832,16 +832,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -909,7 +909,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index fc2854304..c49c5de69 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124291 # Number of seconds simulated -sim_ticks 124290972500 # Number of ticks simulated -final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124349 # Number of seconds simulated +sim_ticks 124348696500 # Number of ticks simulated +final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226846 # Simulator instruction rate (inst/s) -host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103264191 # Simulator tick rate (ticks/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 1203.62 # Real time elapsed on the host +host_inst_rate 233440 # Simulator instruction rate (inst/s) +host_op_rate 280271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106315167 # Simulator tick rate (ticks/s) +host_mem_usage 292792 # Number of bytes of host memory used +host_seconds 1169.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory -system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261040 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory +system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261020 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69987 # Per bank write bursts system.physmem.perBankRdBursts::2 1297 # Per bank write bursts system.physmem.perBankRdBursts::3 10756 # Per bank write bursts -system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::4 42907 # Per bank write bursts system.physmem.perBankRdBursts::5 121816 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 261 # Per bank write bursts -system.physmem.perBankRdBursts::8 228 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 611 # Per bank write bursts +system.physmem.perBankRdBursts::14 657 # Per bank write bursts +system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124290963000 # Total gap between requests +system.physmem.totGap 124348687000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261040 # Read request sizes (log2) +system.physmem.readPktSize::6 261020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation -system.physmem.totQLat 4615275409 # Total ticks spent queuing -system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation +system.physmem.totQLat 4577430956 # Total ticks spent queuing +system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.05 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 1.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193087 # Number of row buffer hits during reads +system.physmem.readRowHits 193077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.avgGap 476395.25 # Average gap between requests system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.097094 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states -system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.069721 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states +system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.140000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35978086 # Number of BP lookups -system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits +system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.109899 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35976625 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,135 +401,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248581946 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248697394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued -system.cpu.iq.rate 1.365233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued +system.cpu.iq.rate 1.364596 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1401 # number of nop insts executed -system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed -system.cpu.iew.exec_branches 31542222 # Number of branches executed -system.cpu.iew.exec_stores 83131698 # Number of stores executed -system.cpu.iew.exec_rate 1.357225 # Inst execution rate -system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153093104 # num instructions producing a value -system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value -system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1402 # number of nop insts executed +system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542264 # Number of branches executed +system.cpu.iew.exec_stores 83131740 # Number of stores executed +system.cpu.iew.exec_rate 1.356592 # Inst execution rate +system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153087171 # num instructions producing a value +system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value +system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,35 +686,35 @@ system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573745483 # The number of ROB reads -system.cpu.rob.rob_writes 686139464 # The number of ROB writes -system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573863058 # The number of ROB reads +system.cpu.rob.rob_writes 686133284 # The number of ROB writes +system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325197340 # number of integer regfile reads -system.cpu.int_regfile_writes 134110925 # number of integer regfile writes -system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads -system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads -system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads +system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325196483 # number of integer regfile reads +system.cpu.int_regfile_writes 134110146 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads +system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542798 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542800 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id @@ -722,121 +722,121 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits -system.cpu.dcache.overall_hits::total 161938775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits +system.cpu.dcache.overall_hits::total 161951039 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses -system.cpu.dcache.overall_misses::total 3884657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses +system.cpu.dcache.overall_misses::total 3871840 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks -system.cpu.dcache.writebacks::total 1542798 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1430654 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910668 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910668 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks +system.cpu.dcache.writebacks::total 1542800 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2341322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2341322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2341322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2341322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220724 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220724 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27108294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27108294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015801 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543319 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543319 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27069234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27069234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844364193 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844364193 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1270000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1270000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -845,397 +845,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20496.323888 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20496.323888 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8361.243884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8361.243884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18760.774160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18760.774160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18761.462693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18761.462693 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726144 # number of replacements -system.cpu.icache.tags.tagsinuse 511.811939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81493663 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726656 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.148889 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 348619500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.811939 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999633 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999633 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20466.744191 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20466.744191 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725912 # number of replacements +system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165181558 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165181558 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81493663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81493663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81493663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81493663 # number of overall hits -system.cpu.icache.overall_hits::total 81493663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733780 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733780 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733780 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733780 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 733780 # number of overall misses -system.cpu.icache.overall_misses::total 733780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8421387941 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8421387941 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11476.720463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11476.720463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11476.720463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11476.720463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits +system.cpu.icache.overall_hits::total 81490807 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses +system.cpu.icache.overall_misses::total 733549 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726144 # number of writebacks -system.cpu.icache.writebacks::total 726144 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7107 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7107 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7107 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7107 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7107 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7107 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726673 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726673 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7893866450 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7893866450 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7893866450 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7893866450 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7893866450 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7893866450 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008837 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008837 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008837 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10863.024290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10863.024290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402240 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402337 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 88 # number of redundant prefetches already in prefetch queue +system.cpu.icache.writebacks::writebacks 725912 # number of writebacks +system.cpu.icache.writebacks::total 725912 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28103 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 28036 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5253.910549 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1811940 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6312 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 287.062738 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5234.159238 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1826320 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6292 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 290.260648 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5156.372421 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 97.538128 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.320673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 189 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5154.317005 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4127 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373718 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70566797 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70566797 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968251 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968251 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1046259 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1046259 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 747 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 544 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010498 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373535 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70559178 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70559178 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968252 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968252 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1046027 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1046027 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219940 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219940 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 697144 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 697144 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094316 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1094316 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 697144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1314256 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2011400 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 697144 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1314256 # number of overall hits -system.cpu.l2cache.overall_hits::total 2011400 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 219941 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219941 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696850 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 696850 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094381 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1094381 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 696850 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1314322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2011172 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 696850 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1314322 # number of overall hits +system.cpu.l2cache.overall_hits::total 2011172 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 790 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 790 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29447 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 29447 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228264 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 228264 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 29447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 229054 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 258501 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 29447 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 229054 # number of overall misses -system.cpu.l2cache.overall_misses::total 258501 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 42000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 42000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71200500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71200500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2623850500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2623850500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17976905500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17976905500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2623850500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18048106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20671956500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2623850500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18048106000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20671956500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 968251 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 968251 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1046259 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1046259 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 789 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 789 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29509 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 29509 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228201 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 228201 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 29509 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 258499 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 29509 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses +system.cpu.l2cache.overall_misses::total 258499 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 69993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2629297500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2629297500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17936282000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17936282000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2629297500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18006275500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20635573000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2629297500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18006275500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20635573000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968252 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968252 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1046027 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1046027 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726591 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 726591 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726591 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1543310 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2269901 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726591 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1543310 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2269901 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726359 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 726359 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322582 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1322582 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726359 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1543312 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2269671 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726359 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1543312 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2269671 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003579 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003579 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040528 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040528 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172590 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172590 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040528 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148417 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.113882 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040528 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148417 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.113882 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2470.588235 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2470.588235 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90127.215190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90127.215190 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89104.170204 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89104.170204 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78754.886885 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78754.886885 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79968.574590 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79968.574590 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003575 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003575 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172542 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172542 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.113893 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113893 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2529.411765 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2529.411765 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88711.660330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88711.660330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89101.545291 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89101.545291 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78598.612627 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78598.612627 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79828.444211 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79828.444211 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 91 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 96 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54078 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 54078 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54181 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 54181 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 739 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 739 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29436 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29436 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228230 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228230 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 29436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 228969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 258405 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 29436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 228969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54078 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 312483 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206290287 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 263000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 263000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65107500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65107500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2446651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2446651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16605070000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16605070000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2446651000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16670177500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19116828500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2446651000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16670177500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19323118787 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29498 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29498 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228899 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228899 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54181 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312578 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203172843 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63769500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63769500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2451726000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2451726000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16564497500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16564497500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2451726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16628267000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19079993000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2451726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16628267000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19283165843 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040512 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172564 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172564 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113840 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137664 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3814.680406 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15470.588235 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15470.588235 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88102.165088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88102.165088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83117.645060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83117.645060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72755.860316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72755.860316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.102939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55629 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260286 # Transaction distribution system.membus.trans_dist::UpgradeReq 17 # Transaction distribution -system.membus.trans_dist::ReadExReq 739 # Transaction distribution -system.membus.trans_dist::ReadExResp 739 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 733 # Transaction distribution +system.membus.trans_dist::ReadExResp 733 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261057 # Request fanout histogram +system.membus.snoop_fanout::samples 261037 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261057 # Request fanout histogram -system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261037 # Request fanout histogram +system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 8f8bc9d4d..bcc6de449 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.339013 # Number of seconds simulated -sim_ticks 339012932000 # Number of ticks simulated -final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.338999 # Number of seconds simulated +sim_ticks 338998876000 # Number of ticks simulated +final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218277 # Simulator instruction rate (inst/s) -host_op_rate 268728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115505586 # Simulator tick rate (ticks/s) -host_mem_usage 277356 # Number of bytes of host memory used -host_seconds 2935.04 # Real time elapsed on the host +host_inst_rate 210128 # Simulator instruction rate (inst/s) +host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111189218 # Simulator tick rate (ticks/s) +host_mem_usage 277020 # Number of bytes of host memory used +host_seconds 3048.85 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory -system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory -system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 957477 # Number of read requests accepted -system.physmem.writeReqs 66339 # Number of write requests accepted -system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory +system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory +system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 956909 # Number of read requests accepted +system.physmem.writeReqs 66317 # Number of write requests accepted +system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19910 # Per bank write bursts -system.physmem.perBankRdBursts::1 19533 # Per bank write bursts -system.physmem.perBankRdBursts::2 657271 # Per bank write bursts -system.physmem.perBankRdBursts::3 20982 # Per bank write bursts -system.physmem.perBankRdBursts::4 19710 # Per bank write bursts -system.physmem.perBankRdBursts::5 21143 # Per bank write bursts -system.physmem.perBankRdBursts::6 19634 # Per bank write bursts -system.physmem.perBankRdBursts::7 20055 # Per bank write bursts -system.physmem.perBankRdBursts::8 19495 # Per bank write bursts -system.physmem.perBankRdBursts::9 20079 # Per bank write bursts -system.physmem.perBankRdBursts::10 19428 # Per bank write bursts -system.physmem.perBankRdBursts::11 19728 # Per bank write bursts -system.physmem.perBankRdBursts::12 19649 # Per bank write bursts -system.physmem.perBankRdBursts::13 21208 # Per bank write bursts -system.physmem.perBankRdBursts::14 19490 # Per bank write bursts -system.physmem.perBankRdBursts::15 19853 # Per bank write bursts -system.physmem.perBankWrBursts::0 4286 # Per bank write bursts +system.physmem.perBankRdBursts::0 19928 # Per bank write bursts +system.physmem.perBankRdBursts::1 19580 # Per bank write bursts +system.physmem.perBankRdBursts::2 657267 # Per bank write bursts +system.physmem.perBankRdBursts::3 20958 # Per bank write bursts +system.physmem.perBankRdBursts::4 19729 # Per bank write bursts +system.physmem.perBankRdBursts::5 20737 # Per bank write bursts +system.physmem.perBankRdBursts::6 19560 # Per bank write bursts +system.physmem.perBankRdBursts::7 19988 # Per bank write bursts +system.physmem.perBankRdBursts::8 19522 # Per bank write bursts +system.physmem.perBankRdBursts::9 20089 # Per bank write bursts +system.physmem.perBankRdBursts::10 19525 # Per bank write bursts +system.physmem.perBankRdBursts::11 19708 # Per bank write bursts +system.physmem.perBankRdBursts::12 19661 # Per bank write bursts +system.physmem.perBankRdBursts::13 21032 # Per bank write bursts +system.physmem.perBankRdBursts::14 19553 # Per bank write bursts +system.physmem.perBankRdBursts::15 19787 # Per bank write bursts +system.physmem.perBankWrBursts::0 4255 # Per bank write bursts system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4145 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4249 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4152 # Per bank write bursts +system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.perBankWrBursts::5 4226 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4149 # Per bank write bursts +system.physmem.perBankWrBursts::15 4152 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 339012921500 # Total gap between requests +system.physmem.totGap 338998865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 957477 # Read request sizes (log2) +system.physmem.readPktSize::6 956909 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66339 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66317 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,187 +149,183 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads -system.physmem.totQLat 27473404757 # Total ticks spent queuing -system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads +system.physmem.totQLat 27417238749 # Total ticks spent queuing +system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 805066 # Number of row buffer hits during reads -system.physmem.writeRowHits 23137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes -system.physmem.avgGap 331126.81 # Average gap between requests -system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.908824 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states -system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states -system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.431501 # Core power per rank (mW) -system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states -system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174656775 # Number of BP lookups -system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits +system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing +system.physmem.readRowHits 804753 # Number of row buffer hits during reads +system.physmem.writeRowHits 22823 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes +system.physmem.avgGap 331304.00 # Average gap between requests +system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.898453 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states +system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states +system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.731167 # Core power per rank (mW) +system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states +system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174659469 # Number of BP lookups +system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -359,7 +355,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -389,7 +385,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,7 +415,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,96 +446,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678025865 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 677997753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available @@ -569,15 +565,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -601,90 +597,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued -system.cpu.iq.rate 1.268433 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued +system.cpu.iq.rate 1.268482 # Inst issue rate +system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9874 # number of nop insts executed -system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed -system.cpu.iew.exec_branches 143381564 # Number of branches executed -system.cpu.iew.exec_stores 152690015 # Number of stores executed -system.cpu.iew.exec_rate 1.253898 # Inst execution rate -system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487342605 # num instructions producing a value -system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10143 # number of nop insts executed +system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed +system.cpu.iew.exec_branches 143380865 # Number of branches executed +system.cpu.iew.exec_stores 152688992 # Number of stores executed +system.cpu.iew.exec_rate 1.253946 # Inst execution rate +system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back +system.cpu.iew.wb_producers 486195731 # num instructions producing a value +system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -734,82 +730,82 @@ system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1524914900 # The number of ROB reads -system.cpu.rob.rob_writes 1798382781 # The number of ROB writes -system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1524889115 # The number of ROB reads +system.cpu.rob.rob_writes 1798376442 # The number of ROB writes +system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868463326 # number of integer regfile reads -system.cpu.int_regfile_writes 500698648 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads -system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes -system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads +system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868460616 # number of integer regfile reads +system.cpu.int_regfile_writes 500698081 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads +system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes +system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756453 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756456 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits -system.cpu.dcache.overall_hits::total 371037940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits +system.cpu.dcache.overall_hits::total 371036694 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses -system.cpu.dcache.overall_misses::total 3446044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses +system.cpu.dcache.overall_misses::total 3446049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -818,470 +814,469 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks -system.cpu.dcache.writebacks::total 2756453 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks +system.cpu.dcache.writebacks::total 2756456 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1979522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1980154 # number of replacements +system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits -system.cpu.icache.overall_hits::total 245757684 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses -system.cpu.icache.overall_misses::total 1983224 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits +system.cpu.icache.overall_hits::total 245752746 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses +system.cpu.icache.overall_misses::total 1983875 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks -system.cpu.icache.writebacks::total 1979522 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks +system.cpu.icache.writebacks::total 1980154 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297323 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297120 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1975820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285803 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1285803 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1975820 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2004463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3980283 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1975820 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2004463 # number of overall hits -system.cpu.l2cache.overall_hits::total 3980283 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 190 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 190 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2186 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2186 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses -system.cpu.l2cache.overall_misses::total 756717 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 64352827500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 735952 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 735952 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3357075 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3357075 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 190 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits +system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses +system.cpu.l2cache.overall_misses::total 756229 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks -system.cpu.l2cache.writebacks::total 66339 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 799 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 799 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks +system.cpu.l2cache.writebacks::total 66317 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1026 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1026 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1825 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1826 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552812 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552356 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 956088 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution -system.membus.trans_dist::CleanEvict 230984 # Transaction distribution -system.membus.trans_dist::UpgradeReq 190 # Transaction distribution -system.membus.trans_dist::ReadExReq 1387 # Transaction distribution -system.membus.trans_dist::ReadExResp 1387 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 955532 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution +system.membus.trans_dist::CleanEvict 230803 # Transaction distribution +system.membus.trans_dist::UpgradeReq 181 # Transaction distribution +system.membus.trans_dist::ReadExReq 1375 # Transaction distribution +system.membus.trans_dist::ReadExResp 1375 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957667 # Request fanout histogram +system.membus.snoop_fanout::samples 957090 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957667 # Request fanout histogram -system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957090 # Request fanout histogram +system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index d9533629f..35c099c69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060131 # Number of seconds simulated -sim_ticks 60130734500 # Number of ticks simulated -final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060132 # Number of seconds simulated +sim_ticks 60131512500 # Number of ticks simulated +final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310652 # Simulator instruction rate (inst/s) -host_op_rate 397278 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263409545 # Simulator tick rate (ticks/s) -host_mem_usage 281384 # Number of bytes of host memory used -host_seconds 228.28 # Real time elapsed on the host +host_inst_rate 320494 # Simulator instruction rate (inst/s) +host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271758284 # Simulator tick rate (ticks/s) +host_mem_usage 281048 # Number of bytes of host memory used +host_seconds 221.27 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory @@ -26,17 +26,17 @@ system.physmem.num_reads::cpu.data 124041 # Nu system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128515 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60130703000 # Total gap between requests +system.physmem.totGap 60131481000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,16 +196,16 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes @@ -227,12 +227,12 @@ system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Wr system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3048956750 # Total ticks spent queuing -system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3049168000 # Total ticks spent queuing +system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s @@ -247,62 +247,62 @@ system.physmem.readRowHits 112228 # Nu system.physmem.writeRowHits 69923 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279590.56 # Average gap between requests +system.physmem.avgGap 279594.18 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.883743 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states +system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) +system.physmem_0.averagePower 386.918165 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.200220 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states +system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) +system.physmem_1.averagePower 383.198268 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14827796 # Number of BP lookups system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120261469 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120263025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695850 # CPI: cycles per instruction -system.cpu.ipc 0.589675 # IPC: instructions per cycle +system.cpu.cpi 1.695872 # CPI: cycles per instruction +system.cpu.ipc 0.589667 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,16 +472,16 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -489,11 +489,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits @@ -502,10 +502,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits -system.cpu.dcache.overall_hits::total 42605457 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits +system.cpu.dcache.overall_hits::total 42605460 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_misses::cpu.data 255005 # n system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +534,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses @@ -548,14 +548,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,16 +582,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136566 system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -602,26 +602,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id @@ -631,7 +631,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits @@ -644,12 +644,12 @@ system.cpu.icache.demand_misses::cpu.inst 45588 # n system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses @@ -662,12 +662,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,34 +682,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 45588 system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy @@ -723,7 +723,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits @@ -752,18 +752,18 @@ system.cpu.l2cache.demand_misses::total 128588 # nu system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses system.cpu.l2cache.overall_misses::total 128588 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) @@ -792,18 +792,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.623805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,18 +836,18 @@ system.cpu.l2cache.demand_mshr_misses::total 128516 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses @@ -862,25 +862,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution @@ -920,7 +920,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26198 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution system.membus.trans_dist::CleanEvict 7237 # Transaction distribution @@ -943,9 +943,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index da2276c3c..ad340b529 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037982 # Number of seconds simulated -sim_ticks 37982056000 # Number of ticks simulated -final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.038007 # Number of seconds simulated +sim_ticks 38007342000 # Number of ticks simulated +final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220867 # Simulator instruction rate (inst/s) -host_op_rate 282464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118308818 # Simulator tick rate (ticks/s) -host_mem_usage 284316 # Number of bytes of host memory used -host_seconds 321.04 # Real time elapsed on the host +host_inst_rate 224949 # Simulator instruction rate (inst/s) +host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120575368 # Simulator tick rate (ticks/s) +host_mem_usage 283980 # Number of bytes of host memory used +host_seconds 315.22 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory -system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222619 # Number of read requests accepted -system.physmem.writeReqs 97298 # Number of write requests accepted -system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222637 # Number of read requests accepted +system.physmem.writeReqs 97253 # Number of write requests accepted +system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9655 # Per bank write bursts -system.physmem.perBankRdBursts::1 9974 # Per bank write bursts -system.physmem.perBankRdBursts::2 12579 # Per bank write bursts -system.physmem.perBankRdBursts::3 25363 # Per bank write bursts -system.physmem.perBankRdBursts::4 17343 # Per bank write bursts -system.physmem.perBankRdBursts::5 22132 # Per bank write bursts -system.physmem.perBankRdBursts::6 11760 # Per bank write bursts -system.physmem.perBankRdBursts::7 14137 # Per bank write bursts -system.physmem.perBankRdBursts::8 11660 # Per bank write bursts -system.physmem.perBankRdBursts::9 15453 # Per bank write bursts -system.physmem.perBankRdBursts::10 11698 # Per bank write bursts -system.physmem.perBankRdBursts::11 11338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9437 # Per bank write bursts -system.physmem.perBankRdBursts::13 9564 # Per bank write bursts -system.physmem.perBankRdBursts::14 9858 # Per bank write bursts -system.physmem.perBankRdBursts::15 20511 # Per bank write bursts -system.physmem.perBankWrBursts::0 5992 # Per bank write bursts -system.physmem.perBankWrBursts::1 6239 # Per bank write bursts -system.physmem.perBankWrBursts::2 6121 # Per bank write bursts -system.physmem.perBankWrBursts::3 6129 # Per bank write bursts -system.physmem.perBankWrBursts::4 6098 # Per bank write bursts -system.physmem.perBankWrBursts::5 6229 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5980 # Per bank write bursts -system.physmem.perBankWrBursts::8 5938 # Per bank write bursts -system.physmem.perBankWrBursts::9 6095 # Per bank write bursts -system.physmem.perBankWrBursts::10 6202 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6046 # Per bank write bursts -system.physmem.perBankWrBursts::13 6090 # Per bank write bursts -system.physmem.perBankWrBursts::14 6173 # Per bank write bursts -system.physmem.perBankWrBursts::15 6015 # Per bank write bursts +system.physmem.perBankRdBursts::0 9656 # Per bank write bursts +system.physmem.perBankRdBursts::1 9952 # Per bank write bursts +system.physmem.perBankRdBursts::2 12608 # Per bank write bursts +system.physmem.perBankRdBursts::3 25349 # Per bank write bursts +system.physmem.perBankRdBursts::4 17405 # Per bank write bursts +system.physmem.perBankRdBursts::5 22083 # Per bank write bursts +system.physmem.perBankRdBursts::6 11752 # Per bank write bursts +system.physmem.perBankRdBursts::7 14068 # Per bank write bursts +system.physmem.perBankRdBursts::8 11731 # Per bank write bursts +system.physmem.perBankRdBursts::9 15466 # Per bank write bursts +system.physmem.perBankRdBursts::10 11740 # Per bank write bursts +system.physmem.perBankRdBursts::11 11331 # Per bank write bursts +system.physmem.perBankRdBursts::12 9464 # Per bank write bursts +system.physmem.perBankRdBursts::13 9568 # Per bank write bursts +system.physmem.perBankRdBursts::14 9844 # Per bank write bursts +system.physmem.perBankRdBursts::15 20483 # Per bank write bursts +system.physmem.perBankWrBursts::0 5965 # Per bank write bursts +system.physmem.perBankWrBursts::1 6210 # Per bank write bursts +system.physmem.perBankWrBursts::2 6157 # Per bank write bursts +system.physmem.perBankWrBursts::3 6128 # Per bank write bursts +system.physmem.perBankWrBursts::4 6115 # Per bank write bursts +system.physmem.perBankWrBursts::5 6243 # Per bank write bursts +system.physmem.perBankWrBursts::6 6020 # Per bank write bursts +system.physmem.perBankWrBursts::7 5952 # Per bank write bursts +system.physmem.perBankWrBursts::8 5952 # Per bank write bursts +system.physmem.perBankWrBursts::9 6130 # Per bank write bursts +system.physmem.perBankWrBursts::10 6213 # Per bank write bursts +system.physmem.perBankWrBursts::11 5918 # Per bank write bursts +system.physmem.perBankWrBursts::12 6006 # Per bank write bursts +system.physmem.perBankWrBursts::13 6051 # Per bank write bursts +system.physmem.perBankWrBursts::14 6145 # Per bank write bursts +system.physmem.perBankWrBursts::15 6027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37982044500 # Total gap between requests +system.physmem.totGap 38007330500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222619 # Read request sizes (log2) +system.physmem.readPktSize::6 222637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97298 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,120 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads -system.physmem.totQLat 8417974819 # Total ticks spent queuing -system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads +system.physmem.totQLat 8329547257 # Total ticks spent queuing +system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 157076 # Number of row buffer hits during reads -system.physmem.writeRowHits 29766 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 118724.68 # Average gap between requests +system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing +system.physmem.readRowHits 157173 # Number of row buffer hits during reads +system.physmem.writeRowHits 29653 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes +system.physmem.avgGap 118813.75 # Average gap between requests system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.691165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states -system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states -system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.127949 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states -system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17071043 # Number of BP lookups -system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits +system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.852702 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states +system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states +system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.602674 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states +system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17074531 # Number of BP lookups +system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,134 +431,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75964113 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 76014685 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -582,91 +581,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued -system.cpu.iq.rate 1.243808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued +system.cpu.iq.rate 1.243037 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14076 # number of nop insts executed -system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207535 # Number of branches executed -system.cpu.iew.exec_stores 20925336 # Number of stores executed -system.cpu.iew.exec_rate 1.233361 # Inst execution rate -system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44951761 # num instructions producing a value -system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 15722 # number of nop insts executed +system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207940 # Number of branches executed +system.cpu.iew.exec_stores 20924850 # Number of stores executed +system.cpu.iew.exec_rate 1.232594 # Inst execution rate +system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44957522 # num instructions producing a value +system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value +system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -716,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164062130 # The number of ROB reads -system.cpu.rob.rob_writes 194125448 # The number of ROB writes -system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 164144701 # The number of ROB reads +system.cpu.rob.rob_writes 194146843 # The number of ROB writes +system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads -system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101982930 # number of integer regfile reads -system.cpu.int_regfile_writes 56612163 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 45 # number of floating regfile writes -system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads -system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads +system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads +system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101986551 # number of integer regfile reads +system.cpu.int_regfile_writes 56614441 # number of integer regfile writes +system.cpu.fp_regfile_reads 62 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes +system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484814 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484796 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits -system.cpu.dcache.overall_hits::total 40308541 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses -system.cpu.dcache.overall_misses::total 1650373 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits +system.cpu.dcache.overall_hits::total 40307627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses +system.cpu.dcache.overall_misses::total 1651331 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks -system.cpu.dcache.writebacks::total 484814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks +system.cpu.dcache.writebacks::total 484796 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447636 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447636 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485322 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485322 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7113004000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7113004000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2350412971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2350412971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001432500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325639 # number of replacements -system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325456 # number of replacements +system.cpu.icache.tags.tagsinuse 510.336563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22103277 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 325967 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.808327 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits -system.cpu.icache.overall_hits::total 22095836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses -system.cpu.icache.overall_misses::total 337513 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits +system.cpu.icache.overall_hits::total 22103280 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses +system.cpu.icache.overall_misses::total 337250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325639 # number of writebacks -system.cpu.icache.writebacks::total 325639 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 823055 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826389 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2921 # number of redundant prefetches already in prefetch queue +system.cpu.icache.writebacks::writebacks 325456 # number of writebacks +system.cpu.icache.writebacks::total 325456 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11268 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11268 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11268 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11268 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11268 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11268 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325982 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 325982 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 325982 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 325982 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 325982 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 325982 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5371171413 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5371171413 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5371171413 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5371171413 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5371171413 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5371171413 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16476.895697 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16476.895697 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 822258 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825535 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 2876 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78691 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 125520 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15698.936659 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 681800 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141835 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.806994 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78497 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125579 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15699.484972 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 681508 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141902 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.802667 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.900184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.953921 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004266 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16288 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15625.141607 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.343365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.953683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004538 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16299 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2543 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 881 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25499859 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25499859 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 257633 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 257633 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 472926 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 472926 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137172 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137172 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289056 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 289056 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255940 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 255940 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 289056 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 393112 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 682168 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 289056 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 393112 # number of overall hits -system.cpu.l2cache.overall_hits::total 682168 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11425 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11425 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37095 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 37095 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80789 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 80789 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 37095 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 92214 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129309 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 37095 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 92214 # number of overall misses -system.cpu.l2cache.overall_misses::total 129309 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1226064500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1226064500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3155473000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 3155473000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6910815500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6910815500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 3155473000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8136880000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11292353000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 3155473000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8136880000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11292353000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 257633 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 257633 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 472926 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 472926 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148597 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148597 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326151 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 326151 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336729 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336729 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 326151 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485326 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 811477 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 326151 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485326 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 811477 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 859 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001465 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25493850 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25493850 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 260429 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 260429 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 469974 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 469974 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137044 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137044 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288848 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 288848 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255916 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 255916 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 288848 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 392960 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 681808 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 288848 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 392960 # number of overall hits +system.cpu.l2cache.overall_hits::total 681808 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 11552 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11552 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37119 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 37119 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80796 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 80796 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 37119 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 92348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129467 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 37119 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 92348 # number of overall misses +system.cpu.l2cache.overall_misses::total 129467 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1233354500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1233354500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3144915500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 3144915500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6919452000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6919452000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 3144915500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8152806500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11297722000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 3144915500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8152806500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11297722000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 260429 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 260429 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 469974 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 469974 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148596 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148596 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325967 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 325967 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 325967 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 811275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 325967 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 811275 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076886 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.076886 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239923 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239923 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113736 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.190004 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159350 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113736 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.190004 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159350 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077741 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.077741 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113873 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113873 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239956 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239956 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113873 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.190287 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159585 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113873 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.190287 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159585 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106765.451870 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106765.451870 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.221585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.221585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85641.021833 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85641.021833 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 452 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97298 # number of writebacks -system.cpu.l2cache.writebacks::total 97298 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3085 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3085 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 119 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 119 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.unused_prefetches 426 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 97253 # number of writebacks +system.cpu.l2cache.writebacks::total 97253 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3091 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3091 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 3204 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3227 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3229 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 3204 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3227 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115310 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 115310 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8340 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8340 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37072 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37072 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80670 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80670 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 37072 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 89010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 126082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 37072 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 89010 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115310 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 241392 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10321796922 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 201500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 722790000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 722790000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2931479000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2931479000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6418843000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6418843000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2931479000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7141633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10073112000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2931479000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7141633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20394908922 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::total 3229 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 114995 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 114995 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8461 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8461 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37094 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37094 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 37094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 89144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 126238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 37094 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 89144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 114995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 241233 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10227090401 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 218000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 218000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 733523000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 733523000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2920395500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2920395500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2920395500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7161099500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10081495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2920395500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7161099500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20308585401 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 272099 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271801 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214278 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution -system.membus.trans_dist::CleanEvict 28222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 8340 # Transaction distribution -system.membus.trans_dist::ReadExResp 8340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution +system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 8461 # Transaction distribution +system.membus.trans_dist::ReadExResp 8461 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222632 # Request fanout histogram +system.membus.snoop_fanout::samples 222651 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222632 # Request fanout histogram -system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222651 # Request fanout histogram +system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 20e951f6a..c13f099b6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150226 # Number of seconds simulated -sim_ticks 1150225722500 # Number of ticks simulated -final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150228 # Number of seconds simulated +sim_ticks 1150227786500 # Number of ticks simulated +final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 386915 # Simulator instruction rate (inst/s) -host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 288133243 # Simulator tick rate (ticks/s) -host_mem_usage 273608 # Number of bytes of host memory used -host_seconds 3991.99 # Real time elapsed on the host +host_inst_rate 394229 # Simulator instruction rate (inst/s) +host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293579950 # Simulator tick rate (ticks/s) +host_mem_usage 273524 # Number of bytes of host memory used +host_seconds 3917.94 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 2064767 # Nu system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2064767 # Number of read requests accepted system.physmem.writeReqs 1060156 # Number of write requests accepted system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue @@ -61,10 +61,10 @@ system.physmem.perBankRdBursts::8 132488 # Pe system.physmem.perBankRdBursts::9 134781 # Per bank write bursts system.physmem.perBankRdBursts::10 133246 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::12 134523 # Per bank write bursts system.physmem.perBankRdBursts::13 134597 # Per bank write bursts system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130646 # Per bank write bursts +system.physmem.perBankRdBursts::15 130647 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 67159 # Pe system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150225621500 # Total gap between requests +system.physmem.totGap 1150227685500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,25 +194,25 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes @@ -222,24 +222,24 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads -system.physmem.totQLat 59945214750 # Total ticks spent queuing -system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads +system.physmem.totQLat 59946131250 # Total ticks spent queuing +system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s @@ -250,58 +250,58 @@ system.physmem.busUtilRead 0.90 # Da system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775403 # Number of row buffer hits during reads -system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHits 775435 # Number of row buffer hits during reads +system.physmem.writeRowHits 420473 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.avgGap 368081.93 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.667814 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states -system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.679083 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states +system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.748583 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019882 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.746535 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019900 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -309,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300451445 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300455573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489387 # CPI: cycles per instruction -system.cpu.ipc 0.671417 # IPC: instructions per cycle +system.cpu.cpi 1.489389 # CPI: cycles per instruction +system.cpu.ipc 0.671416 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits -system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits +system.cpu.dcache.overall_hits::total 624493045 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses -system.cpu.dcache.overall_misses::total 9590309 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses +system.cpu.dcache.overall_misses::total 9590308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,10 +542,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses @@ -556,14 +556,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,12 +574,12 @@ system.cpu.dcache.writebacks::writebacks 3670055 # nu system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses @@ -590,16 +590,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,24 +610,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id @@ -635,15 +635,15 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits -system.cpu.icache.overall_hits::total 466274661 # number of overall hits +system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits +system.cpu.icache.overall_hits::total 466274758 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses @@ -656,12 +656,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 74803000 system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses @@ -706,16 +706,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2032334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy @@ -729,7 +729,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits @@ -758,18 +758,18 @@ system.cpu.l2cache.demand_misses::total 2064773 # nu system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) @@ -798,18 +798,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.223823 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,18 +838,18 @@ system.cpu.l2cache.demand_mshr_misses::total 2064767 system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses @@ -864,25 +864,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution @@ -922,7 +922,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1252444 # Transaction distribution system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution @@ -945,9 +945,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3e40b495b..413bb751f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787742 # Number of seconds simulated -sim_ticks 787742202500 # Number of ticks simulated -final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787540 # Number of seconds simulated +sim_ticks 787540181500 # Number of ticks simulated +final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 267668 # Simulator instruction rate (inst/s) -host_op_rate 288372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136513298 # Simulator tick rate (ticks/s) -host_mem_usage 329792 # Number of bytes of host memory used -host_seconds 5770.44 # Real time elapsed on the host +host_inst_rate 265954 # Simulator instruction rate (inst/s) +host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135604104 # Simulator tick rate (ticks/s) +host_mem_usage 328428 # Number of bytes of host memory used +host_seconds 5807.64 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236035776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63780672 # Number of bytes read from this memory -system.physmem.bytes_read::total 299882112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104579136 # Number of bytes written to this memory -system.physmem.bytes_written::total 104579136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3688059 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996573 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 83357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299635814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80966428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380685599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 83357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 83357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132758072 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132758072 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132758072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 83357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299635814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80966428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513443671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685658 # Number of read requests accepted -system.physmem.writeReqs 1634049 # Number of write requests accepted -system.physmem.readBursts 4685658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299378880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 503232 # Total number of bytes read from write queue -system.physmem.bytesWritten 104576512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299882112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104579136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7863 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 17 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory +system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory +system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4686888 # Number of read requests accepted +system.physmem.writeReqs 1634386 # Number of write requests accepted +system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue +system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301431 # Per bank write bursts -system.physmem.perBankRdBursts::1 301123 # Per bank write bursts -system.physmem.perBankRdBursts::2 285299 # Per bank write bursts -system.physmem.perBankRdBursts::3 287676 # Per bank write bursts -system.physmem.perBankRdBursts::4 288751 # Per bank write bursts -system.physmem.perBankRdBursts::5 286469 # Per bank write bursts -system.physmem.perBankRdBursts::6 281133 # Per bank write bursts -system.physmem.perBankRdBursts::7 278330 # Per bank write bursts -system.physmem.perBankRdBursts::8 294107 # Per bank write bursts -system.physmem.perBankRdBursts::9 299584 # Per bank write bursts -system.physmem.perBankRdBursts::10 292343 # Per bank write bursts -system.physmem.perBankRdBursts::11 297976 # Per bank write bursts -system.physmem.perBankRdBursts::12 299704 # Per bank write bursts -system.physmem.perBankRdBursts::13 299189 # Per bank write bursts -system.physmem.perBankRdBursts::14 294388 # Per bank write bursts -system.physmem.perBankRdBursts::15 290292 # Per bank write bursts -system.physmem.perBankWrBursts::0 103694 # Per bank write bursts -system.physmem.perBankWrBursts::1 101682 # Per bank write bursts -system.physmem.perBankWrBursts::2 99052 # Per bank write bursts -system.physmem.perBankWrBursts::3 99844 # Per bank write bursts -system.physmem.perBankWrBursts::4 99095 # Per bank write bursts -system.physmem.perBankWrBursts::5 98699 # Per bank write bursts -system.physmem.perBankWrBursts::6 102473 # Per bank write bursts -system.physmem.perBankWrBursts::7 104090 # Per bank write bursts -system.physmem.perBankWrBursts::8 105068 # Per bank write bursts -system.physmem.perBankWrBursts::9 104102 # Per bank write bursts -system.physmem.perBankWrBursts::10 101990 # Per bank write bursts -system.physmem.perBankWrBursts::11 102510 # Per bank write bursts -system.physmem.perBankWrBursts::12 102612 # Per bank write bursts -system.physmem.perBankWrBursts::13 102296 # Per bank write bursts -system.physmem.perBankWrBursts::14 104281 # Per bank write bursts -system.physmem.perBankWrBursts::15 102520 # Per bank write bursts +system.physmem.perBankRdBursts::0 302302 # Per bank write bursts +system.physmem.perBankRdBursts::1 301952 # Per bank write bursts +system.physmem.perBankRdBursts::2 285792 # Per bank write bursts +system.physmem.perBankRdBursts::3 288384 # Per bank write bursts +system.physmem.perBankRdBursts::4 288196 # Per bank write bursts +system.physmem.perBankRdBursts::5 285903 # Per bank write bursts +system.physmem.perBankRdBursts::6 281854 # Per bank write bursts +system.physmem.perBankRdBursts::7 277846 # Per bank write bursts +system.physmem.perBankRdBursts::8 294690 # Per bank write bursts +system.physmem.perBankRdBursts::9 300083 # Per bank write bursts +system.physmem.perBankRdBursts::10 291836 # Per bank write bursts +system.physmem.perBankRdBursts::11 298648 # Per bank write bursts +system.physmem.perBankRdBursts::12 299589 # Per bank write bursts +system.physmem.perBankRdBursts::13 298339 # Per bank write bursts +system.physmem.perBankRdBursts::14 293778 # Per bank write bursts +system.physmem.perBankRdBursts::15 289840 # Per bank write bursts +system.physmem.perBankWrBursts::0 103932 # Per bank write bursts +system.physmem.perBankWrBursts::1 101641 # Per bank write bursts +system.physmem.perBankWrBursts::2 99135 # Per bank write bursts +system.physmem.perBankWrBursts::3 99721 # Per bank write bursts +system.physmem.perBankWrBursts::4 98850 # Per bank write bursts +system.physmem.perBankWrBursts::5 98703 # Per bank write bursts +system.physmem.perBankWrBursts::6 102612 # Per bank write bursts +system.physmem.perBankWrBursts::7 104045 # Per bank write bursts +system.physmem.perBankWrBursts::8 105476 # Per bank write bursts +system.physmem.perBankWrBursts::9 104249 # Per bank write bursts +system.physmem.perBankWrBursts::10 101862 # Per bank write bursts +system.physmem.perBankWrBursts::11 102612 # Per bank write bursts +system.physmem.perBankWrBursts::12 102593 # Per bank write bursts +system.physmem.perBankWrBursts::13 102283 # Per bank write bursts +system.physmem.perBankWrBursts::14 104155 # Per bank write bursts +system.physmem.perBankWrBursts::15 102465 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787742161500 # Total gap between requests +system.physmem.totGap 787540140500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685658 # Read request sizes (log2) +system.physmem.readPktSize::6 4686888 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2727854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1051064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 158136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 89940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634386 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,42 +149,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 108778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -198,133 +198,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4258602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.856263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.818587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.740363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3399214 79.82% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 662534 15.56% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94110 2.21% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35203 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22640 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12473 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7407 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5223 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19798 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4258602 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.747867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.462080 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95523 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1197 1.22% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 705 0.72% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 407 0.42% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 106 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 17 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97968 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97968 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.678997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.638691 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.208217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70313 71.77% 71.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1920 1.96% 73.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17565 17.93% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5314 5.42% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1711 1.75% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 637 0.65% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 262 0.27% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 130 0.13% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 63 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97968 # Writes before turning the bus around for reads -system.physmem.totQLat 162666982970 # Total ticks spent queuing -system.physmem.totMemAccLat 250375639220 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23388975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34774.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads +system.physmem.totQLat 162188930459 # Total ticks spent queuing +system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53524.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing -system.physmem.readRowHits 1712898 # Number of row buffer hits during reads -system.physmem.writeRowHits 340301 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing +system.physmem.readRowHits 1713351 # Number of row buffer hits during reads +system.physmem.writeRowHits 339452 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.83 # Row buffer hit rate for writes -system.physmem.avgGap 124648.53 # Average gap between requests -system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15106540680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8029309200 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16494913680 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4221043380 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59407414560.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64582002630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1606944480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 223006056720 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 35875852320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16122239730 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444464207160 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.225454 # Core power per rank (mW) -system.physmem_0.totalIdleTime 641904162368 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1401750889 # Time in different power states -system.physmem_0.memoryStateTime::REF 25151370000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59428702250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 93425472309 # Time in different power states -system.physmem_0.memoryStateTime::ACT 119284909993 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 489049997059 # Time in different power states -system.physmem_1.actEnergy 15299891880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8132085390 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16904542620 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4308478380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58934141760.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64765265610 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1612336320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219700492200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35552759520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18091245240 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443312102310 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.762917 # Core power per rank (mW) -system.physmem_1.totalIdleTime 641480248383 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1450220904 # Time in different power states -system.physmem_1.memoryStateTime::REF 24952394000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67105561000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92583809905 # Time in different power states -system.physmem_1.memoryStateTime::ACT 119858377963 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 481791838728 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286283098 # Number of BP lookups -system.cpu.branchPred.condPredicted 223408244 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630421 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158004936 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150354998 # Number of BTB hits +system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes +system.physmem.avgGap 124585.67 # Average gap between requests +system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.334256 # Core power per rank (mW) +system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states +system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states +system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states +system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.622143 # Core power per rank (mW) +system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states +system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286296319 # Number of BP lookups +system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.158418 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643073 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3065 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1898 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1167 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 134 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -354,7 +353,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -384,7 +383,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,7 +413,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,133 +444,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575484406 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575080364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928690 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067537239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286283098 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166999969 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546809233 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29285745 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 303 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 986 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656964714 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1575382084 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.406011 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492942163 31.29% 31.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465443083 29.54% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428647 6.44% 67.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515568191 32.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1575382084 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181711 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74686824 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577980395 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849907031 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58165638 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642196 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42200734 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 724 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037196735 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52499519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642196 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139768268 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 492678513 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15538 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837819054 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90458515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976393108 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26740093 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45400307 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1723349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29315109 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985867653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128208959 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432891999 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310968708 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 176 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111448171 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542564068 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199306440 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26831952 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28868587 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947979256 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 230 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857513748 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13517148 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283947070 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647252748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1575382084 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.179088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151868 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 176 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622503864 39.51% 39.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326012726 20.69% 60.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378121823 24.00% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219723484 13.95% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29014011 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1575382084 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166098751 40.96% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2024 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460455 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47920650 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138250302 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801028 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -595,90 +594,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532139508 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186322803 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 32 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued -system.cpu.iq.rate 1.179011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405481927 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709408400 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262995524 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 151 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued +system.cpu.iq.rate 1.179307 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66715 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13309 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24459395 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4550351 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4849996 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642196 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25436916 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1454941 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947979633 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542564068 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199306440 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 168 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1294449 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13309 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700831 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404595 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827842620 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516961097 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29671128 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 147 # number of nop insts executed -system.cpu.iew.exec_refs 698716504 # number of memory reference insts executed -system.cpu.iew.exec_branches 229543654 # Number of branches executed -system.cpu.iew.exec_stores 181755407 # Number of stores executed -system.cpu.iew.exec_rate 1.160178 # Inst execution rate -system.cpu.iew.wb_sent 1808745333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805717319 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169202335 # num instructions producing a value -system.cpu.iew.wb_consumers 1689603795 # num instructions consuming a value -system.cpu.iew.wb_rate 1.146135 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691998 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258049766 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 146 # number of nop insts executed +system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed +system.cpu.iew.exec_branches 229547821 # Number of branches executed +system.cpu.iew.exec_stores 181753477 # Number of stores executed +system.cpu.iew.exec_rate 1.160472 # Inst execution rate +system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169243033 # num instructions producing a value +system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value +system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629745 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1535892995 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083430 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009496 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955612705 62.22% 62.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250634240 16.32% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110090472 7.17% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55300497 3.60% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29246766 1.90% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34056030 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24731317 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18107101 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58113867 3.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1535892995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -728,78 +727,78 @@ system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58113867 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399860729 # The number of ROB reads -system.cpu.rob.rob_writes 3883658641 # The number of ROB writes -system.cpu.timesIdled 841 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102322 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399506472 # The number of ROB reads +system.cpu.rob.rob_writes 3883723576 # The number of ROB writes +system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020020 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020020 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175838440 # number of integer regfile reads -system.cpu.int_regfile_writes 1261579513 # number of integer regfile writes +system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads +system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965813253 # number of cc regfile reads -system.cpu.cc_regfile_writes 551861987 # number of cc regfile writes -system.cpu.misc_regfile_reads 675852638 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads +system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes +system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003360 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638058665 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003872 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524316 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 83293500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999928 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999928 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003339 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335696042 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335696042 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469342719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469342719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168715791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168715791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638058510 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638058510 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638058510 # number of overall hits -system.cpu.dcache.overall_hits::total 638058510 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417195 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417195 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3870256 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3870256 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits +system.cpu.dcache.overall_hits::total 638066980 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287451 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287451 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287453 # number of overall misses -system.cpu.dcache.overall_misses::total 21287453 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440618340000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157333375444 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 245500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 597951715444 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 597951715444 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 597951715444 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 597951715444 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486759914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486759914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses +system.cpu.dcache.overall_misses::total 21287628 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -808,14 +807,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659345961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659345961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659345963 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659345963 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses @@ -824,56 +823,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 61375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28089.399499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28089.396859 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21254267 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3791320 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 940376 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67438 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.601882 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.219342 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003360 # number of writebacks -system.cpu.dcache.writebacks::total 17003360 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3150878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132695 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1132695 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks +system.cpu.dcache.writebacks::total 17003339 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4283573 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4283573 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4283573 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4283573 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266317 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266317 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737561 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737561 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003878 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003878 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003879 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003879 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475470134300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475470209300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -882,401 +881,400 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24834.865228 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24834.865228 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44261.323967 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44261.323967 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27962.452700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 445.623702 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656963104 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 610560.505576 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 587 # number of replacements +system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.623702 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313930500 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313930500 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656963104 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656963104 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656963104 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656963104 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656963104 # number of overall hits -system.cpu.icache.overall_hits::total 656963104 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1608 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1608 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1608 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1608 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1608 # number of overall misses -system.cpu.icache.overall_misses::total 1608 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127367486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127367486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127367486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127367486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127367486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127367486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656964712 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656964712 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656964712 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656964712 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656964712 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656964712 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits +system.cpu.icache.overall_hits::total 656980742 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses +system.cpu.icache.overall_misses::total 1590 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79208.635572 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 79208.635572 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 79208.635572 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 79208.635572 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21110 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 109.378238 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 35.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 589 # number of writebacks -system.cpu.icache.writebacks::total 589 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 531 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 531 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 531 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 531 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 531 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 531 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92273990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 92273990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92273990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 92273990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92273990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 92273990 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 587 # number of writebacks +system.cpu.icache.writebacks::total 587 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85676.870938 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85676.870938 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11610963 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11639700 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19388 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4657940 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647528 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.760193 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13267468 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4663442 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.844995 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4648753 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15649.753914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.006278 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 144 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15770 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 430 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4072 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2569 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1578 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008789 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962524 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561783529 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561783529 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4825740 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4825740 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12156985 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12156985 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1756408 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1756408 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 50 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 50 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11511753 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11511753 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 50 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13268161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13268211 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 50 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13268161 # number of overall hits -system.cpu.l2cache.overall_hits::total 13268211 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 981196 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 981196 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1027 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1027 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754515 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2754515 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3735711 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3736738 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3735711 # number of overall misses -system.cpu.l2cache.overall_misses::total 3736738 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 148500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 148500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104535366500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104535366500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90830000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 90830000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256701151000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 256701151000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 90830000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 361236517500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 361327347500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 90830000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 361236517500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 361327347500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4825740 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4825740 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12156985 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12156985 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 7 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 7 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737604 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737604 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1077 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266268 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266268 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17003872 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17004949 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17003872 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17004949 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 15649.436196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2624 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1515 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007935 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561782498 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561782498 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 4829115 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4829115 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12153582 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12153582 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1756982 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1756982 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509164 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11509164 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13266146 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13266203 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13266146 # number of overall hits +system.cpu.l2cache.overall_hits::total 13266203 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980646 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980646 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1018 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1018 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2757059 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2757059 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3737705 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3738723 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1018 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3737705 # number of overall misses +system.cpu.l2cache.overall_misses::total 3738723 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 212000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 212000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104379369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104379369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90393500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 90393500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256509677500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 256509677500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90393500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 360889047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 360979440500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90393500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 360889047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 360979440500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829115 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4829115 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12153582 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12153582 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1075 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266223 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266223 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17003851 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17004926 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17003851 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17004926 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358414 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358414 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.953575 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.953575 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193079 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193079 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.953575 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219698 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219744 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.953575 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219698 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219744 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21214.285714 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21214.285714 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106538.720602 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106538.720602 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88442.064265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88442.064265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93192.867347 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93192.867347 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88442.064265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96698.196809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96695.927705 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88442.064265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96698.196809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96695.927705 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 541 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358210 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358210 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946977 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946977 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193258 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193258 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946977 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219861 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946977 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219861 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21200 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21200 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106439.397601 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106439.397601 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88795.186640 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88795.186640 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93037.427745 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93037.427745 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96551.533906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96551.533906 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 135.250000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 58311 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 1634049 # number of writebacks -system.cpu.l2cache.writebacks::total 1634049 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3931 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3931 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 58324 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 1634386 # number of writebacks +system.cpu.l2cache.writebacks::total 1634386 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3928 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3928 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45060 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45060 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45589 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45589 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 48991 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 48992 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 48991 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 48992 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1197394 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1197394 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977265 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 977265 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1026 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1026 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709455 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709455 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3686720 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3687746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3686720 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1197394 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4885140 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84175133455 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 106500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 106500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98289203000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98289203000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84580000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84580000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237438885500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237438885500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84580000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335728088500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 335812668500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84580000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335728088500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 419987801955 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1196489 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976718 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 976718 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2711470 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2711470 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3688188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3689205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3688188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4885694 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84134366845 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98135216000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98135216000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84211500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84211500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237209473000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237209473000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84211500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335344689000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335428900500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84211500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335344689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356978 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356978 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.952646 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189920 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189920 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216863 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287278 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008905 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003965 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 200821 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6459789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12178209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3013479 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1493524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266268 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176463552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176570112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6141063 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104579840 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23146008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009594 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097477 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22923954 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 222053 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23146008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008401540 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 16551 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1614499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505814993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9333193 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668760 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634049 # Transaction distribution -system.membus.trans_dist::CleanEvict 3013479 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 977434 # Transaction distribution -system.membus.trans_dist::ReadExResp 977434 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14018850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14018850 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404461184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404461184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3710005 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution +system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 976882 # Transaction distribution +system.membus.trans_dist::ReadExResp 976882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685665 # Request fanout histogram +system.membus.snoop_fanout::samples 4686898 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685665 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685665 # Request fanout histogram -system.membus.reqLayer0.occupancy 17659262741 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4686898 # Request fanout histogram +system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25448696800 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 17a991711..5040af9e4 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086155 # Number of seconds simulated -sim_ticks 86154694000 # Number of ticks simulated -final_tick 86154694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086149 # Number of seconds simulated +sim_ticks 86149358000 # Number of ticks simulated +final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235949 # Simulator instruction rate (inst/s) -host_op_rate 248729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117978801 # Simulator tick rate (ticks/s) -host_mem_usage 272668 # Number of bytes of host memory used -host_seconds 730.26 # Real time elapsed on the host +host_inst_rate 240669 # Simulator instruction rate (inst/s) +host_op_rate 253706 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120331720 # Simulator tick rate (ticks/s) +host_mem_usage 272336 # Number of bytes of host memory used +host_seconds 715.93 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 193344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory -system.physmem.bytes_read::total 916864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652480 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7573354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2244149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 824563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10642067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7573354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7573354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7573354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2244149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 824563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10642067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14326 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory +system.physmem.bytes_read::total 916736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14324 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14326 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916864 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916864 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1380 # Per bank write bursts +system.physmem.perBankRdBursts::0 1375 # Per bank write bursts system.physmem.perBankRdBursts::1 498 # Per bank write bursts -system.physmem.perBankRdBursts::2 5094 # Per bank write bursts -system.physmem.perBankRdBursts::3 810 # Per bank write bursts +system.physmem.perBankRdBursts::2 5101 # Per bank write bursts +system.physmem.perBankRdBursts::3 808 # Per bank write bursts system.physmem.perBankRdBursts::4 2279 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts system.physmem.perBankRdBursts::9 231 # Per bank write bursts -system.physmem.perBankRdBursts::10 355 # Per bank write bursts -system.physmem.perBankRdBursts::11 347 # Per bank write bursts -system.physmem.perBankRdBursts::12 322 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 320 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts system.physmem.perBankRdBursts::14 240 # Per bank write bursts system.physmem.perBankRdBursts::15 797 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86154635500 # Total gap between requests +system.physmem.totGap 86149299500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14326 # Read request sizes (log2) +system.physmem.readPktSize::6 14324 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,16 +95,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -191,26 +191,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.983974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.597492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.302837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5884 69.34% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2105 24.81% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 256 3.02% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 62 0.73% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39 0.46% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 0.44% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 16 0.19% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9 0.11% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 78 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8486 # Bytes accessed per row activation -system.physmem.totQLat 1505073312 # Total ticks spent queuing -system.physmem.totMemAccLat 1773685812 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 105058.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation +system.physmem.totQLat 1500750524 # Total ticks spent queuing +system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123808.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s @@ -219,68 +219,68 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5836 # Number of row buffer hits during reads +system.physmem.readRowHits 5833 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6013865.38 # Average gap between requests -system.physmem.pageHitRate 40.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51536520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27380925 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 6014332.55 # Average gap between requests +system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5189405520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121826120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 276469440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12277996650 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8345487360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9295531755 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36669774810 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.627121 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82968376764 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 533443000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2206916000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34311542002 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21733088112 # Time in different power states -system.physmem_0.memoryStateTime::ACT 444281236 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26925423650 # Time in different power states +system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.565010 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states +system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20199060 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 885081600.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198834810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 51009600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1986610170 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1389476160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18829930140 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23375329815 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.318119 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85585158757 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101660000 # Time in different power states -system.physmem_1.memoryStateTime::REF 376638000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77610163250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3618418671 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91210493 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4356603586 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85641138 # Number of BP lookups -system.cpu.branchPred.condPredicted 68185958 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5937589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39953535 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38189781 # Number of BTB hits +system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.290305 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states +system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85639426 # Number of BP lookups +system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.585487 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3685328 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81910 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681706 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653811 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27895 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40302 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,97 +401,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172309389 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172298717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5689865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347272234 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85641138 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42528920 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158389740 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11889123 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4192 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78352490 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18126 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170032695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18322538 10.78% 10.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071394 17.69% 28.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31619936 18.60% 47.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90018827 52.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170032695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497020 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.015399 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17554898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18106153 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121828666 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6773205 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5769773 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11065170 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189895 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 305047176 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240886 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5769773 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37541623 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8963730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601187 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108324902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8831480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277455959 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13183896 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3097230 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842604 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2610060 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40707 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26842 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481461567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187957820 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296507996 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005110 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188484638 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23627 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13450862 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33923289 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14424821 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2554501 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1823311 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263831896 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45982 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214447255 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5189742 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82241924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216953797 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170032695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.261212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018500 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53222567 31.30% 31.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36044522 21.20% 52.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65538005 38.54% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13630055 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1551450 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45818 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 278 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170032695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35671912 66.13% 66.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153261 0.28% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available @@ -512,24 +512,24 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35713 0.07% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 264 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 557 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40113 0.07% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13911271 25.79% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3849843 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 142059 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136275 0.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167013253 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919503 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245720 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460387 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31297547 14.59% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13233764 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576685 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147618 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214447255 # Type of FU issued -system.cpu.iq.rate 1.244548 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53942541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251542 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654066032 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344116098 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204293302 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3993456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010644 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266215456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2174340 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590107 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued +system.cpu.iq.rate 1.244603 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6027145 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7088 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1780187 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25576 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5769773 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5628686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175497 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263897928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33923289 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14424821 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23574 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3848 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 168493 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7088 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148569 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6396009 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207164807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30640004 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7282448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20050 # number of nop insts executed -system.cpu.iew.exec_refs 43787631 # number of memory reference insts executed -system.cpu.iew.exec_branches 44861497 # Number of branches executed -system.cpu.iew.exec_stores 13147627 # Number of stores executed -system.cpu.iew.exec_rate 1.202284 # Inst execution rate -system.cpu.iew.wb_sent 206408899 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206099654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129383753 # num instructions producing a value -system.cpu.iew.wb_consumers 221651913 # num instructions consuming a value -system.cpu.iew.wb_rate 1.196102 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583725 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68705367 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20111 # number of nop insts executed +system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed +system.cpu.iew.exec_branches 44861358 # Number of branches executed +system.cpu.iew.exec_stores 13146949 # Number of stores executed +system.cpu.iew.exec_rate 1.202341 # Inst execution rate +system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129381204 # num instructions producing a value +system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value +system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5762801 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158729167 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.144404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74124112 46.70% 46.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41154034 25.93% 72.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22561648 14.21% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9505511 5.99% 92.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552884 2.24% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129952 1.34% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1300201 0.82% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1012623 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3388202 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158729167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3388202 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405691473 # The number of ROB reads -system.cpu.rob.rob_writes 512028923 # The number of ROB writes -system.cpu.timesIdled 10004 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2276694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405673353 # The number of ROB reads +system.cpu.rob.rob_writes 512011515 # The number of ROB writes +system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.000037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.000037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.999963 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.999963 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218765999 # number of integer regfile reads -system.cpu.int_regfile_writes 114196362 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903942 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441736 # number of floating regfile writes -system.cpu.cc_regfile_reads 708332294 # number of cc regfile reads -system.cpu.cc_regfile_writes 229516818 # number of cc regfile writes -system.cpu.misc_regfile_reads 57457287 # number of misc regfile reads +system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218762027 # number of integer regfile reads +system.cpu.int_regfile_writes 114194444 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes +system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads +system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes +system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72598 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.401142 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41046057 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73110 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.428765 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 556160500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.401142 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72586 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -722,347 +722,347 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82390572 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82390572 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28659846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28659846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341293 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341293 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41001139 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41001139 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41001503 # number of overall hits -system.cpu.dcache.overall_hits::total 41001503 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22994 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22994 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits +system.cpu.dcache.overall_hits::total 41000964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112414 # number of overall misses -system.cpu.dcache.overall_misses::total 112414 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1992894500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1992894500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 247642499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 247642499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2317500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2317500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2240536999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2240536999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2240536999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2240536999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28749150 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28749150 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses +system.cpu.dcache.overall_misses::total 112371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41113437 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41113437 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41113917 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41113917 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22315.848114 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22315.848114 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10769.874706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10769.874706 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8913.461538 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8913.461538 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19951.708837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19951.708837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19931.120670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19931.120670 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11146 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 867 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.855825 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72598 # number of writebacks -system.cpu.dcache.writebacks::total 72598 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24877 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24877 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14424 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14424 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks +system.cpu.dcache.writebacks::total 72586 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64427 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8570 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8570 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72997 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72997 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73110 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73110 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88387499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88387499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150873499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1150873499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151842499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16491.315753 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16491.315753 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10313.593816 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10313.593816 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.038317 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.038317 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15754.924073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15754.924073 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53656 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578461 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78294727 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1445.405535 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85384212500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578461 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53582 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156759076 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156759076 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78294727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78294727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78294727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78294727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78294727 # number of overall hits -system.cpu.icache.overall_hits::total 78294727 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57727 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57727 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57727 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57727 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57727 # number of overall misses -system.cpu.icache.overall_misses::total 57727 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2248583426 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2248583426 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2248583426 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2248583426 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2248583426 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2248583426 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78352454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78352454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78352454 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78352454 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78352454 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78352454 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38952.022901 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38952.022901 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38952.022901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38952.022901 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93736 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits +system.cpu.icache.overall_hits::total 78288973 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses +system.cpu.icache.overall_misses::total 57655 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3241 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.921938 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53656 # number of writebacks -system.cpu.icache.writebacks::total 53656 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54169 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54169 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54169 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54169 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54169 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54169 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2054126952 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2054126952 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2054126952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2054126952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2054126952 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2054126952 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37920.710222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37920.710222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified +system.cpu.icache.writebacks::writebacks 53582 # number of writebacks +system.cpu.icache.writebacks::total 53582 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1351 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1796.196657 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99029 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2833 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.955524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.103732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.092925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004217 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 127 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007751 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4005715 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4005715 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64715 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64715 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 51058 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 51058 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8400 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8400 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43969 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43969 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61680 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61680 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43969 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70080 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 114049 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43969 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70080 # number of overall hits -system.cpu.l2cache.overall_hits::total 114049 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10200 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10200 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2794 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2794 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10200 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3030 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13230 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10200 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3030 # number of overall misses -system.cpu.l2cache.overall_misses::total 13230 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 21058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1711516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1711516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 557966500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 557966500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1711516500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 579024500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2290541000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1711516500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 579024500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2290541000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 64715 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 64715 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 51058 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 51058 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8636 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8636 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54169 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 54169 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64474 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 64474 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54169 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73110 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 127279 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54169 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73110 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 127279 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027327 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027327 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188300 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188300 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043335 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043335 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.041444 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103945 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.041444 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103945 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89228.813559 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89228.813559 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167795.735294 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167795.735294 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199701.682176 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199701.682176 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 173132.350718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 173132.350718 # average overall miss latency +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007996 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165100 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4002973 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4002973 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64701 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64701 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 50991 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 50991 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8404 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8404 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43901 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 43901 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61671 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 61671 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 43901 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 70075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 113976 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 43901 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 70075 # number of overall hits +system.cpu.l2cache.overall_hits::total 113976 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 230 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 230 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10194 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10194 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10194 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3023 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 13217 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10194 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3023 # number of overall misses +system.cpu.l2cache.overall_misses::total 13217 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20353000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 20353000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1710678000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1710678000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 556147500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 556147500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1710678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 576500500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2287178500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1710678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 576500500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2287178500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 64701 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 64701 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 50991 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 50991 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54095 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54095 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64464 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64464 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54095 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73098 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 127193 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54095 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73098 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 127193 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.026639 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.026639 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188446 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188446 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043327 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043327 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188446 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.041355 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103913 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188446 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.041355 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103913 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88491.304348 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88491.304348 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167812.242496 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167812.242496 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199121.911923 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199121.911923 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 173048.233336 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 173048.233336 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,136 +1081,136 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2053 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 2053 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10195 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10195 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2786 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2786 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10195 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3021 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 13216 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10195 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3021 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15269 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99413611 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1649486500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1649486500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 540711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 540711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1649486500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 560135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2209622000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1649486500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 560135500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2309035611 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2048 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2048 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 229 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 229 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10189 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10189 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10189 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 13203 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10189 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15251 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 98123639 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1648684500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1648684500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 538898000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 538898000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1648684500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 557669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2206353500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1648684500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 557669000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2304477139 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027212 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188207 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043211 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043211 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103835 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188354 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043202 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119965 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 48423.580614 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82655.319149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82655.319149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161793.673369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161793.673369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194081.658291 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194081.658291 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167192.947942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151223.761281 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253533 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126274 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 943 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 942 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64474 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218818 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6900736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9325312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16226048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2391 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2398 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088263 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283705 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118226 91.17% 91.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11443 8.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129670 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 253020500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81260982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109669990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14326 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10488 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14090 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28651 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14094 # Transaction distribution +system.membus.trans_dist::ReadExReq 229 # Transaction distribution +system.membus.trans_dist::ReadExResp 229 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14326 # Request fanout histogram +system.membus.snoop_fanout::samples 14324 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14326 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14326 # Request fanout histogram -system.membus.reqLayer0.occupancy 18054137 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14324 # Request fanout histogram +system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77252283 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index ed017dd04..4554501a1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103189 # Number of seconds simulated -sim_ticks 103189362000 # Number of ticks simulated -final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103324 # Number of seconds simulated +sim_ticks 103323995500 # Number of ticks simulated +final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113263 # Simulator instruction rate (inst/s) -host_op_rate 189839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88494148 # Simulator tick rate (ticks/s) -host_mem_usage 308956 # Number of bytes of host memory used -host_seconds 1166.06 # Real time elapsed on the host +host_inst_rate 113414 # Simulator instruction rate (inst/s) +host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88727502 # Simulator tick rate (ticks/s) +host_mem_usage 308112 # Number of bytes of host memory used +host_seconds 1164.51 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory -system.physmem.bytes_read::total 362816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5669 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory +system.physmem.bytes_read::total 363712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5683 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 384 # Per bank write bursts -system.physmem.perBankRdBursts::2 476 # Per bank write bursts -system.physmem.perBankRdBursts::3 363 # Per bank write bursts -system.physmem.perBankRdBursts::4 357 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 419 # Per bank write bursts -system.physmem.perBankRdBursts::7 395 # Per bank write bursts -system.physmem.perBankRdBursts::8 387 # Per bank write bursts +system.physmem.perBankRdBursts::0 307 # Per bank write bursts +system.physmem.perBankRdBursts::1 383 # Per bank write bursts +system.physmem.perBankRdBursts::2 475 # Per bank write bursts +system.physmem.perBankRdBursts::3 366 # Per bank write bursts +system.physmem.perBankRdBursts::4 364 # Per bank write bursts +system.physmem.perBankRdBursts::5 336 # Per bank write bursts +system.physmem.perBankRdBursts::6 422 # Per bank write bursts +system.physmem.perBankRdBursts::7 392 # Per bank write bursts +system.physmem.perBankRdBursts::8 390 # Per bank write bursts system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 260 # Per bank write bursts -system.physmem.perBankRdBursts::11 268 # Per bank write bursts -system.physmem.perBankRdBursts::12 228 # Per bank write bursts -system.physmem.perBankRdBursts::13 486 # Per bank write bursts -system.physmem.perBankRdBursts::14 420 # Per bank write bursts -system.physmem.perBankRdBursts::15 286 # Per bank write bursts +system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::11 273 # Per bank write bursts +system.physmem.perBankRdBursts::12 229 # Per bank write bursts +system.physmem.perBankRdBursts::13 485 # Per bank write bursts +system.physmem.perBankRdBursts::14 425 # Per bank write bursts +system.physmem.perBankRdBursts::15 285 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103189107000 # Total gap between requests +system.physmem.totGap 103323737000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5669 # Read request sizes (log2) +system.physmem.readPktSize::6 5683 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation -system.physmem.totQLat 180648250 # Total ticks spent queuing -system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation +system.physmem.totQLat 187208250 # Total ticks spent queuing +system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -215,311 +215,311 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4421 # Number of row buffer hits during reads +system.physmem.readRowHits 4417 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18202347.33 # Average gap between requests -system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18181196.02 # Average gap between requests +system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) -system.physmem_0.averagePower 248.859682 # Core power per rank (mW) -system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states -system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states -system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.195533 # Core power per rank (mW) +system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states +system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states +system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.957187 # Core power per rank (mW) -system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40834752 # Number of BP lookups -system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups +system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.066219 # Core power per rank (mW) +system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40855234 # Number of BP lookups +system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206378725 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206647992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 759085 19.25% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2706167 68.61% 87.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 429953 10.90% 98.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 45275 1.15% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3569 0.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82580981 24.41% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26493050 7.83% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1734957 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 130131 0.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued -system.cpu.iq.rate 1.639065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3944049 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011660 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879529534 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8195011 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336881361 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4119124 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued +system.cpu.iq.rate 1.636375 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed -system.cpu.iew.exec_branches 18920718 # Number of branches executed -system.cpu.iew.exec_stores 25631647 # Number of stores executed -system.cpu.iew.exec_rate 1.581303 # Inst execution rate -system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256417161 # num instructions producing a value -system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value -system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed +system.cpu.iew.exec_branches 18918443 # Number of branches executed +system.cpu.iew.exec_stores 25617475 # Number of stores executed +system.cpu.iew.exec_rate 1.578731 # Inst execution rate +system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256328359 # num instructions producing a value +system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value +system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,469 +569,469 @@ system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 646691809 # The number of ROB reads -system.cpu.rob.rob_writes 1022946396 # The number of ROB writes -system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647170594 # The number of ROB reads +system.cpu.rob.rob_writes 1023323556 # The number of ROB writes +system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524499390 # number of integer regfile reads -system.cpu.int_regfile_writes 288922915 # number of integer regfile writes -system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads -system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes -system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads -system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes -system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads +system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524350393 # number of integer regfile reads +system.cpu.int_regfile_writes 288862618 # number of integer regfile writes +system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads +system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes +system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads +system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes +system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 81 # number of replacements -system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 82 # number of replacements +system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits -system.cpu.dcache.overall_hits::total 82760268 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses -system.cpu.dcache.overall_misses::total 3278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits +system.cpu.dcache.overall_hits::total 82730262 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses +system.cpu.dcache.overall_misses::total 3314 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000100 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 626 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 632 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 585 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2061 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2061 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2646 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2646 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2646 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2646 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 134984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202072500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 202072500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 202072500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 202072500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000100 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 664 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 664 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2041 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2650 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2650 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2650 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2650 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70639000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70639000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 134072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204711000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204711000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204711000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204711000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000099 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 114681.196581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 114681.196581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65494.420184 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65494.420184 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6530 # number of replacements -system.cpu.icache.tags.tagsinuse 1674.310192 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41178058 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4834.240197 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6640 # number of replacements +system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8628 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4776.846430 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1674.310192 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.817534 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.817534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1671.571610 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.816197 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.816197 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 841 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 742 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82391597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82391597 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41178058 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41178058 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41178058 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41178058 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41178058 # number of overall hits -system.cpu.icache.overall_hits::total 41178058 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13213 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13213 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13213 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13213 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13213 # number of overall misses -system.cpu.icache.overall_misses::total 13213 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 660957500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 660957500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 660957500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 660957500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 660957500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 660957500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41191271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41191271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41191271 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41191271 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41191271 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41191271 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000321 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000321 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000321 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000321 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000321 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000321 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50023.272535 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50023.272535 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50023.272535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50023.272535 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1885 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 842 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 82465000 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82465000 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 41214631 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41214631 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41214631 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41214631 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41214631 # number of overall hits +system.cpu.icache.overall_hits::total 41214631 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13297 # number of overall misses +system.cpu.icache.overall_misses::total 13297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 657223000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 657223000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 657223000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 657223000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 657223000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 657223000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41227928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41227928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41227928 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41227928 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41227928 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41227928 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000323 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000323 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000323 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000323 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000323 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000323 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49426.411973 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49426.411973 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49426.411973 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49426.411973 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2020 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.833333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 842 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6530 # number of writebacks -system.cpu.icache.writebacks::total 6530 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4157 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4157 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4157 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4157 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4157 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4157 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9056 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9056 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9056 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9056 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9056 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9056 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 451350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 451350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 451350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 451350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 451350000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 451350000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000220 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000220 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49839.885159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49839.885159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.125000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6640 # number of writebacks +system.cpu.icache.writebacks::total 6640 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9145 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9145 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9145 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9145 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9145 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9145 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 457240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 457240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457240000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 457240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49998.906506 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49998.906506 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3894.223765 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12041 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5669 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.124008 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3890.572014 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12247 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5683 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.155024 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2411.748228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.475537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073601 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.118842 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5669 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1008 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 525 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3930 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173004 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147349 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147349 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6476 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6476 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 541 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 541 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2409.860843 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1480.711171 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.118731 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5683 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1019 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 527 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3926 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173431 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149123 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149123 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 17 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 17 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6583 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6583 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 523 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 523 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 65 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 65 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4949 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72 # number of overall hits -system.cpu.l2cache.overall_hits::total 4949 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1515 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1515 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3636 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3636 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 518 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 518 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3636 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2033 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5669 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3636 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2033 # number of overall misses -system.cpu.l2cache.overall_misses::total 5669 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125752500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125752500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 385523500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 385523500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 65306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 65306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 385523500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 191058500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576582000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 385523500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 191058500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576582000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6476 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6476 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 541 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 541 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8513 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8513 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 583 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 583 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8513 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 10618 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8513 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 10618 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995401 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.995401 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.427111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.427111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888508 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888508 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.427111 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.965796 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.533905 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.427111 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.965796 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.533905 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83004.950495 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83004.950495 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106029.565457 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106029.565457 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 126073.359073 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 126073.359073 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 101707.884989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 101707.884989 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4982 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4982 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 75 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 75 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4982 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 82 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5064 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4982 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 82 # number of overall hits +system.cpu.l2cache.overall_hits::total 5064 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1513 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1513 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3638 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3638 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3638 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5683 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3638 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2045 # number of overall misses +system.cpu.l2cache.overall_misses::total 5683 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125080500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 125080500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 390212000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 390212000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68692500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 68692500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 390212000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 193773000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 583985000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 390212000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 193773000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 583985000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 17 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 17 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6583 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6583 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 523 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 523 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1520 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1520 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8620 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8620 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8620 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2127 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10747 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8620 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2127 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10747 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995395 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.995395 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.422042 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.422042 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.876442 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.876442 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.422042 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.961448 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.528799 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.422042 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.961448 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.528799 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82670.522141 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82670.522141 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107260.032985 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107260.032985 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 129121.240602 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 129121.240602 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 102759.985923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 102759.985923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5669 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3636 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2033 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5669 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110602500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110602500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 349163500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 349163500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 60126000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 60126000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 349163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 543 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 525 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4154 # Transaction distribution -system.membus.trans_dist::ReadExReq 1515 # Transaction distribution -system.membus.trans_dist::ReadExResp 1515 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4170 # Transaction distribution +system.membus.trans_dist::ReadExReq 1513 # Transaction distribution +system.membus.trans_dist::ReadExResp 1513 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5669 # Request fanout histogram +system.membus.snoop_fanout::samples 5683 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5669 # Request fanout histogram -system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5683 # Request fanout histogram +system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |